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| exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com XR17V252 66 mhz pci bus dual uart with power management support march 2006 rev. 1.0.1 general description the XR17V252 1 (v252) is a single chip 2-channel 66mhz pci uart (universal asynchronous receiver and transmitter) solution, optimized for higher performance and lower power. the v252 device with its fifth generation register set is designed to meet the high bandwidth and power management requirements for multi-serial communication ports for system administration and management. the 32-bit 66mhz pci interface is compliant with pci 3.0 and pci power management revision 1.1 specifications. the device provides an upgrade path for exar?s 33mhz 5v and universal pci uart family. the v252 consists of two independent uart channels, each with set of configuration and enhanced registers, 64 bytes of transmit (tx) and receive (rx) fifos, and a fractional baud rate generator (brg). a global interrupt source register provides a complete interrupt status indication for both channels to speed up interrupt parsing. the v252 device operates at 33/66mhz and features fully programmable tx and rx fifo level triggers, automatic hardware and software flow control, and automatic rs-485 half duplex direction control output for software and hardware design simplification. n ote 1: covered by u.s. patents #5,649,122 and #5,949,787 applications ? remote access servers ? storage network management ? factory automation and process control ? instrumentation ? multi-port rs-232/rs-422/rs-485 cards ? point-of-sale systems features ? high performance 32-bit 66mhz pci uart ? pci 3.0 compliant ? pci power management rev. 1.1 compliant ? eeprom interface for pci configuration ? 3.3v supply with 5v tolerant non-pci (serial) inputs ? data read/write burst operation ? global interrupt register for both uart channels ? up to 8 mbps serial data rate ? eight multi-purpose inputs/outputs ? a 16-bit general purpose timer/counter ? sleep mode with wake-up indicator ? two independent uart channels controlled with 16c550 compatible register set 64-byte tx and rx fifos with level counters and programmable trigger levels fractional baud rate generator automatic rts/cts or dtr/dsr hardware flow control with programmable hysteresis automatic xon/xoff software flow control rs-485 half duplex direction control output with selectable tu rn-around delay ? infrared (irda 1.0) data encoder/decoder f igure 1. b lock d iagram of the XR17V252 tmrck device configuration registers xtal1 xtal2 crystal osc / buffer tx0 , rx0 , dtr0#, dsr0 #, rts0#, cts0 #, cd0 #, ri0# pci local bus interface clk ( up to 66 mhz) configuration space registers . mpio0- mpio7 multi-purpose inputs/ outputs tx1 , rx1 , dtr1#, dsr1 #, rts1#, cts1 #, cd1 #, ri1# 16-bit timer/counter eeck eedi eedo eecs eeprom interface (5 v tolerant serial inputs) enir uart channel 0 64 byte tx fifo 64 byte rx fifo brg ir endec tx & rx uart regs uart channel 1 64 byte tx fifo 64 byte rx fifo brg ir endec tx & rx uart regs en485# 3.3 v vcc rst# ad[31:0] c/be[3:0]# par frame# irdy# trdy# devsel# stop# idsel perr# serr# inta# pme#
XR17V252 2 66 mhz pci bus dual uart with power management support rev. 1.0.1 f igure 2. p in o ut of the XR17V252 ordering information p art n umber p ackage o perating t emperature r ange d evice s tatus XR17V252im 100-lead tqfp -40c to +85c active mpio0 mpio1 vcc gnd ad24 c/be3# idsel vcc eecs eedi eeck eedo vcc pme# xtal1 xtal2 mpio2 mpio3 rx1 cts1# tx1 dtr1# rts1# ri1# cd1# dsr1# rx0 cts0# dsr0# cd0# ri0# rts0# dtr0# tx0 ad26 ad27 ad28 ad29 ad30 ad31 vcc gnd clk rst# inta# ad25 mpio5 tmrck enir vcc gnd mpio7 mpio6 mpio4 gnd ad11 ad10 ad9 ad8 vcc gnd c/be0# ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 vcc 27 26 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 50 49 48 en485# nc gnd nc devsel# 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 gnd gnd ad23 ad22 ad21 ad20 ad19 ad18 ad17 ad16 c/be2# frame# irdy# trdy# vcc stop# perr# serr# par c/be1# ad15 ad14 ad13 ad12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 53 54 55 56 57 58 59 60 61 62 63 64 51 52 75 74 73 72 71 70 67 68 69 66 65 xr17v 252 100-tqfp (14x14x1.0mm) XR17V252 3 rev. 1.0.1 66 mhz pci bus dual uart with power management support pin descriptions n ame p in # t ype d escription pci local bus interface rst# 86 i pci bus reset input (active low). it re sets the pci local bus configuration space registers, device configuration registers and uart channel registers to the default condition, see table 21 . clk 87 i pci bus clock input of up to 66.67mhz. ad31-ad24, ad23-ad16, ad15-ad8, ad7-ad0 90-97, 2-9, 24-31, 35-42 i/o address data lines [31:0] (bidirectional). frame# 13 i bus transaction cycle frame (active lo w). it indicates t he beginning and dura - tion of an access. c/be3# - c/be0# 98, 12, 21, 34 i bus command/byte enable [3:0] (active low). this line is multiplexed for bus command during the address phase and byte enables during the data phase. irdy# 14 i initiator ready (active low). during a wr ite, it indicates that valid data is present on data bus. during a read, it i ndicates the master is ready to accept data. trdy# 15 o target ready (active low). stop# 17 o target request to stop current transaction (active low). idsel 99 i initialization device select (active high). devsel# 16 o device select to the XR17V252 (active low). inta# 85 od device interrupt from XR17V252 (open drain, active low). par 20 i/o parity is even across ad[31:0] and c/be[ 3:0]#. (bidirectional, active high). perr# 18 o data parity error indicator, except for special cycle transactions (active low). optional in bus target application. serr# 19 od system error indicator, address parity or data parity during special cycle transactions (open drain, active low) . optional in bus target application. modem or serial i/o interface tx0 73 o uart channel 0 transmit data or infrar ed transmit data. normal txd output idles high while infrared txd output idles low. rx0 66 i uart channel 0 receive data or infrared receive data. normal rxd input idles high while infrared rxd input id les low. in the infrared mode, the polarity of the incoming rxd signal can be selected via fctr bit-4. if this bit is a logic 0, a low on the rxd input is c onsidered a mark and if this bit is a logic 1, a high on the rxd input is considered a space. rts0# 71 o uart channel 0 request to send or gener al purpose output (active low). if this output is not used, leave it unconnected. cts0# 67 i uart channel 0 clear to send or general purpose input (active low). this input should be connected to vcc when not used. dtr0# 72 o uart channel 0 data terminal ready or general purpose output (active low). if this output is not used, leave it unconnected. XR17V252 4 66 mhz pci bus dual uart with power management support rev. 1.0.1 dsr0# 68 i uart channel 0 data set ready or general purpose input (active low). this input should be connected to vcc when not used. cd0# 69 i uart channel 0 carrier detect or general purpose input (active low). this input should be connected to vcc when not used. ri0# 70 i uart channel 0 ring indicator or general purpose input (active low). this input should be connected to vcc when not used. tx1 62 o uart channel 1 transmit data or infr ared transmit data. normal txd output idles high while infrared txd output idles low. rx1 55 i uart channel 1 receive data or infrared receive data. normal rxd input idles high while infrared rxd input id les low. in the infrared mode, the polarity of the incoming rxd signal can be selected via fctr bit-4. if this bit is a logic 0, a low on the rxd input is c onsidered a mark and if this bit is a logic 1, a high on the rxd input is considered a space. rts1# 60 o uart channel 1 request to send or g eneral purpose output (active low). if this output is not used, leave it unconnected. cts1# 56 i uart channel 1 clear to send or general purpose input (active low). this input should be connected to vcc when not used. dtr1# 61 o uart channel 1 data terminal ready or general purpose output (active low). if this output is no t used, leave it unconnected. dsr1# 57 i uart channel 1 data set ready or general purpose input (active low). this input should be connected to vcc when not used. cd1# 58 i uart channel 1 carrier detect or general purpose input (active low). this input should be connected to vcc when not used. ri1# 59 i uart channel 1 ring indicator or general purpose input (active low). this input should be connected to vcc when not used. ancillary signals mpio0-mpio7 52-45 i/o multi-purpose inputs/outputs 0-7. the function of these pin are defined thru the configuration register mpios el, mpiolvl, mpioinv, mpio3t and mpioint eeck 84 o serial clock to eeprom. an internal clock of clk divide by 256 is used for reading the vendor and sub-vendor id during power up or reset. however, it can be manually clocked thru the configuration register regb. eecs 83 o chip select to a eeprom device like 93c 46. it is manually selectable thru the configuration register regb. requir es a pull-up 4.7k ohm resister for external sensing of eeprom during power up. see dan112 for further details. eedi 82 o write data to eeprom device. it is m anually accessible thru the configura - tion register regb. the v252 auto-c onfiguration register interface logic uses the 16-bit format. eedo 81 i read data from eeprom device. it is manually accessible thru the configu - ration register regb. xtal1 77 i crystal or external clock input. xtal2 76 o crystal or buffered clock output. tmrck 75 i 16-bit timer/counter external clock input. pin descriptions n ame p in #t ype d escription XR17V252 5 rev. 1.0.1 66 mhz pci bus dual uart with power management support n ote : pin type: i=input, o=output, i/o= input/output, od=output open drain. enir 74 i global infrared mode enable (active high). this pin is sampled during power up, following a hardware reset (rst#) or soft-reset (register reset). it can be used to start up both uarts in the infrared mode. the sampled logic state is transferred to mcr bit-6 in the uart. software can override this pin there - after and enable or disable it. en485# 65 i global autors485 half-duplex direction control enable (active low). during power up or reset, this pin is sampled and if it is a logic high, both uarts are set for auto rs485 mode. al so, the auto rs485 bit, fctr[5], is set in both channels. software can override this pin thereafter and enable or disable it. pme# 79 od power management event signal. while in d3 hot state, if the pme_enable bit in the power management control/status register is set, the v252 asserts the pme# upon receiving a new character or upon change of state of modem inputs on any channel. vcc 54, 80, 10, 22, 32, 43, 89, 100 pwr power supply for the uart core logic and pci bus i/o - 3.3v only. the v252 is pci 3.0 signalling compliant at 3.3v operation. the non-pci inputs (except xtal1) are 5v tolerant. this includes all the serial (modem) inputs. gnd 1, 11, 23, 33, 44, 53, 78, 88 pwr power supply common, ground. nc 63, 64 no connection. pin descriptions n ame p in #t ype d escription XR17V252 6 66 mhz pci bus dual uart with power management support rev. 1.0.1 functional description the XR17V252 (v252) consists of two enhanced 1655 0 uarts with a conventional pci interface and a non- volatile memory interface for pci plug-and-play auto-conf iguration. the pci local bu s is a synchronous timing bus where all bus transactions are associated with the bus clock. the v252 supports 66mhz clock and 32-bit wide read and write data transfer operations including data burst mode through the pci interface. read and write data operations may be in byte, word or double-wo rd (dword) format. the device consists of three sets of registers: ? pci local bus configuration registers for pci auto configuration ? 32-bit global device configuration re gisters for overall control and monitoring of the 2 uart channels. ? a combination set of the 16c550 compatible registers and enhanced registers in each of the individual uart channel, for control, status, and byte wide data transfer each uart channel has 64-byte fifos, automatic rts/cts or dtr/dsr hardware flow control with hysteresis control, automatic xon/xoff software flow control, programmable transmit and receive fifo trigger level, fifo level counters, infrared encoder and decode r (irda ver. 1.0), and a programmable fractional baud rate generator with a prescaler of 1x or 4x, and data rate up to 6.25 mbps at 8x sampling clock.the XR17V252 is available in a 100-pin tqfp (14x14x1.0mm) industrial grade package. pci l ocal b us i nterface this is the host interface and it me ets the pci local bus specification revi sion 3.0. the pci local bus operations are synchronous, where each transaction is associated to the bus cl ock. the v252 can operate with the bus clock of up to a 66.67mhz. data transfers operation can be formatted in 8-bit, 16-bit, 24-bit or 32-bit wide. with 32-bit data operations, it pushes the data transfer ra te on the bus up to 264 mbyte/sec. this increases the overall system?s communication performance up to 32 ti mes better than the 8-bit i sa bus. see pci local bus specification revision 3.0 for bus operation details. pci l ocal b us c onfiguration s pace r egisters a set of pci local bus configuration space register is provided. these registers provide the pci local bus operating system with the card?s vendor id, device id, sub-vendor id, product model number, and resources and capabilities. the pci local bus oper ating system collects this data from all the card s on the bus during the auto configuration phase that follows immediately after a power up or system reset/reboot. after it has sorted out all devices on the bus, it defines and download the ope rating conditions to the ca rds. one of the definitions is the base address loaded into the base address register (bar) where th e card will be operating in the pci local bus memory space. all this is described in more detail in ?section 1.1, pci local bus configuration space registers? on page 7 . p ower m anagement r egisters this set of registers is a continuati on of the configuration space and provides status and control of power management functions of the v252. the power mana gement capabilities (pmc) register and the power management control/status regist er (pmcsr) are implemented. ?section 1.2, power management registers? on page 9 describes these registers and details how power management is implemented in the device. eeprom i nterface an external 93c46 eeprom is used to store 8 words of information. details of this information can be found in ?section 1.4, eeprom interface? on page 12 . this information is only used with the plug-and-play auto configuration of the pci local bus. these data provide automatic hardware installation onto the pci bus. the eeprom interface consists of 4 si gnals, eedi, eedo, eecs, and eeck. the eeprom is not needed when auto configuration is not required in the application. ho wever, if your design requires non-volatile memory for other purpose, it is poss ible to store and retrieve data on t he eeprom through a sp ecial pci device configuration register. see application note dan112 for its programming details. XR17V252 7 rev. 1.0.1 66 mhz pci bus dual uart with power management support 1.0 XR17V252 internal registers the XR17V252 uart has three different sets of registers as shown in figure 3 . the pci local bus configuration space registers are for plug-and-play auto-configuration when connecting the device to a the pci bus. this auto-configuration featur e makes installation very easy into a pci system and it is part of the pci local bus specification. the second register set is the device configuration registers that are also accessible directly from the pci bus for programmi ng general operating condi tions of the device and monitoring the status of various functions common to both channels. these functions include both channel uarts? interrupt control and status, 16-bit general purpose timer control and status, multipurpose inputs/ outputs control and status, sleep mode, soft-reset, and device identification and revision. and lastly, each uart channel has its own set of internal uart configuration registers for its own operation control and status reporting. all 4 sets of channel registers are em bedded inside the device configuration registers space, which provides faster access. the second and third set of registers are mapped into 1k of the pci bus memory address space. the following paragraphs describe all 3 sets of registers in detail. 1.1 pci local bus configuration space registers the pci local bus configuration space registers are responsible for setting up the device?s operating environment in the pci local bus. the pre-defined operat ing parameters of the device is read by the pci bus plug-and-play auto- configuration manag er in the operating system. after the pci bus has collected all data from every device/card on the bus, it defines and dow nloads the memory mapping information to each device/ card about their individual operation memory address location and conditions. the operating memory mapped address location is downloaded into the base address regi ster (bar) register, located at an address offset of 0x10 in the configuration space. custom modification of certain registers is possible by using an external 93c46 eeprom. the eeprom contains th e device vendor and su b-vendor data, along with 6 other words of information (see ?section 1.4, eeprom interface? on page 12 ) required by the auto-configuration setup. f igure 3. t he XR17V252 r egister s ets channel 0 int, mpio, timer, reg device configuration and uart[7:0] configuration registers are mapped on to the base address register (bar) in a 1k- byte of memory address space pci local bus interface channel 0 channel 1 device configuration registers 2 channel interrupts, multipurpose i/os, 16-bit timer/counter, sleep, reset, dvid, drev uart[1:0] configuration registers 16550 compatible and exar enhanced registers pci local bus configuration space registers for plug- and-play auto configuration vendor and sub-vendor id and product model number in external eeprom 0x0000 0x0200 0x03ff 0x0080 XR17V252 8 66 mhz pci bus dual uart with power management support rev. 1.0.1 t able 1: pci l ocal b us c onfiguration s pace r egisters a ddress o ffset b its t ype d escription r eset v alue ( hex or binary ) 0x00 31:16 ewr device id (exar device id number) 0x0252 15:0 ewr vendor id (exar) specified by pcisig 0x13a8 0x04 31 30 29:28 rwc rwc ro parity error detected. cleared by writing a logic 1. system error detected. cleared by writing a logic 1. unused 0b 0b 00b 27 ro target abort. 0b 26:25 ro devsel# timing. 00b 24 ro unemployments bus master error reporting bit 0b 23 ro fast back to back transactions are supported 1b 22 ro reserved status bit 0b 21 ro 66mhz capable 1b 20 ro capabilities list 1b 19:16 ro reserved status bits 0000b 15:9,7, 5,4,3,2 ro command bits (reserved) 0x0000 8 rwr serr# driver enable. logic 1=enable driver and 0=disable driver 0b 6 rwr parity error enable. logic 1=respond to parity error and 0=ignore 0b 1 rwr command controls a device?s response to mem space accesses: 0=disable mem space accesses, 1=enable mem space accesses 0b 0 ro device?s response to i/o space accesses is disabled. (0 = disable i/o space accesses) 0b 0x08 31:8 ewr class code (default is ?simpl e 550 communication controller?) 0x070002 7:0 ro revision id (exar devi ce revision number) current rev. value 0x0c 31:24 ro bist (built-in self test) 0x00 23:16 ro header type (a single function device with one bar) 0x00 15:8 ro unimplemented latency timer (needed only for bus master) 0x00 7:0 ro unimplemented cache line size 0x00 0x10 31:10 rwr memory base address register (bar) 0x00 9:0 ro claims a 1k address space for the memory mapped uarts 0x000 0x14 31:0 ro unimplemented base addre ss register (returns zeros) 0x00000000 0x18h 31:0 ro unimplemented base addre ss register (returns zeros) 0x00000000 0x1c 31:0 ro unimplemented base addre ss register (returns zeros) 0x00000000 0x20 31:0 ro unimplemented base addre ss register (returns zeros) 0x00000000 XR17V252 9 rev. 1.0.1 66 mhz pci bus dual uart with power management support n ote : ewr=read/write from external eepr om. rwr=read/write from ad[31:0]. ro= read only. rwc=read/write- clear. 1.2 power management registers the power management registers are implemented in 2 dwords starting at address offset 0x40 of the pci local bus configuration space. the bit defi nitions of these registers are shown in table 2 below. the v252 complies with revision 1.1 of the pci power management interface specification. 0x24 31:0 ro unimplemented base addre ss register (returns zeros) 0x00000000 0x28 31:0 ro reserved 0x00000000 0x2c 31:16 ewr subsystem id (write from external eeprom by customer) 0x0000 15:0 ewr subsystem vendor id (write from external eeprom by cus - tomer) 0x0000 0x30 31:0 ro expansion rom base address (unimplemented) 0x00000000 0x34 31:8 ro reserved (returns zeros) 0x000000 7:0 ro capability pointer (implemented for power management) 0x40 0x38 31:0 ro reserved (returns zeros) 0x00000000 0x3c 31:24 ro unimplemented maxlat 0x00 23:16 ro unimplemented mingnt 0x00 15:8 ro interrupt pin, use inta#. 0x01 7:0 rwr interrupt line. 0xxx t able 2: p ower m anagement r egisters a ddress o ffset b its t ype d escription r eset v alue ( hex or binary ) 0x40 31:16 see below power management capabilities (pmc) see below 31:27 ro pme support (pme# can be asserted from d3 hot only) 01000b 26:20 ro reserved or not supported 0000000b 19 ro pme clock (pci clock is required for pme# generation) 1b 18:16 ro version 010b 15:8 ro next item pointer 0x00 7:0 ro capability id 0x01 0x44 31:24 ro unimplemented data register 0x00 23:16 ro unimplemented bridge support extensions 0x00 15:0 see below power management control/st atus register (pmcsr) see below 15 rwc pme_status 0b t able 1: pci l ocal b us c onfiguration s pace r egisters a ddress o ffset b its t ype d escription r eset v alue ( hex or binary ) XR17V252 10 66 mhz pci bus dual uart with power management support rev. 1.0.1 n ote : rwr=read/write from ad[31:0]. ro= read only. rwc=read/write-clear. 1.2.1 power states and power state transitions of the v252 the XR17V252 supports d0, d3 hot and d3 cold power states and is capable of generating the pme# signal from the d3 hot state. the following paragraphs describe these power states and figure 4 shows the power state transitions of the v252. d0 s tate the XR17V252 must be placed in the d0 state before being used in a system. the d0 state represents two states - d0 uninitalized and d0 active. upon entering d0 from power up or transition from d3 hot , the v252 will be in the d0 uninitialized state. once initialized by the system software, the v252 will enter the d0 active state. in the d0 active state, the v252 is fully functional and will respond to all pci bus transactions as well as issue interrupts (inta#). the system software can program the v252 to enter the d3 hot state from the d0 state. d3 hot s tate the v252 enters the d3 hot state when the system software programs the v252 from d0 to d3 hot . in this state, the v252 will not be fully functional. t he v252 will respond only to pci conf iguration space accesses, if a pci clock is provided and will no t respond to pci memory accesses nor will it issue interrupts. however, the v252 will continue to receive data and the au tomatic software and hardware flow co ntrol, if enabled, will continue to function normally. while in the d3 hot state, the v252 asserts the pme# (power management event) signal, if enabled by setting pme_enable bit, upon one of the following events: rx pin of any of the channels go es low (start bit detected), or any of the delta bits of modem inputs (msr register bits [3:0]) is set in any of the 2 channels (see page 48 ) the v252 also sets the pme_status bit when such an event occurs, regardless of whether the pme_enable bit is set or not. the system software can reset the pme_status bit by writing a ?1? to it . when the system software programs the v252 from d3 hot to d0 , typically in response to the pm e# signal, the v252 enters the d0 active state and will retain all the values of it s internal registers. the v252 will keep its pci sign al drivers disabled for the duration of the d3 hot to d0 uninitialized state transition. the v252 saves the pme context (configuration registers and functional state information) in the d3 hot state. note: the v252 has a sleep mode which keeps the power consumption to a minimum (see sleep mode description on page 20 ). this is independent of the power state the v252 is in. the user can optionally place the v252 in sleep mode (via the software driver) in the active d0 state anytime or specifically when the system software commands the v252 to enter the d3 hot state. the crystal oscillator s huts down when the conditions given in sleep mode section on page 20 are satisfied, and re-starts when one of the events as described in the same section occurs. upon re-starting, the oscillator may take a long time to settle. this time may be more than 20ms which is the maximum wait time guarantee d by the system software before resuming normal pci bus transactions in the active d0 state. therefore, there may be data errors if the v252 is commanded to transmit data before t he oscillator is ready. it is recommended not to use sleep mode while in the d3 hot state for this reason. 14:9 ro reserved 00000b 8 rwr pme_enable 0b 7:2 ro reserved 000000b 1:0 rwr powerstate 00b t able 2: p ower m anagement r egisters a ddress o ffset b its t ype d escription r eset v alue ( hex or binary ) XR17V252 11 rev. 1.0.1 66 mhz pci bus dual uart with power management support d3 cold s tate the v252 enters the state when power is removed from the device. all context is lost in this state and the v252 does not support pme# in this state. when power is restored, pci rst# must be asserted and the v252 will return to the d0 uninitialized state with a full pci 3.0 compliant powe r-on reset sequence. the v252 will set all its registers and outputs to the power-on defaults just as at initial power up. the system software must then fully initialize and re-configure the v252 to place it in the d0 active state. 1.3 special read/write register to store user information this 32-bit register can be used to store user inform ation and is writable only via the eeprom. this is implemented at an offset of 0x48 in the pci co nfiguration space immediately following the power management registers. this register can be used to store applic ation-specific information which may be used by the device driver to initialize the device appropriately. n ote : ewr=read/write from external eeprom. f igure 4. p ower s tate t ransitions of the XR17V252 t able 3: s pecial r ead /w rite r egister a ddress o ffset b its t ype d escription r eset v alue ( hex ) 0x48 31:0 ewr user information writable only through eeprom 0x00000000 d0 uninitialized d3 hot d3 cold d0 active power on + pci rst# power on + pci rst# vcc removed XR17V252 12 66 mhz pci bus dual uart with power management support rev. 1.0.1 1.4 eeprom interface the v252 provides an interf ace to an electrically erasable program mable read only memo ry (eeprom). the eeprom must be a 93c46-like device, with its memory conf igured as 16-bit words. th is interface is provided in order to program the registers in the pci configuration space of the pci uart during power-up. the following table gives the mapping of the eeprom memory to the register s in the v252?s pci configuration space. when the pci rst# is negated, the v252 will download the da ta from the eeprom, if it detects a high on the eecs pin. the v252 takes a maximum of 2 16 pci clocks from the rising edge of the pci rst# signal to read the eeprom data. for more details on th e eeprom interface, please refer to the application note dan112 on exar?s website. n ote : * only the upper 8 bits in this word in eeprom location are used and the lower 8 bits are ignored. the lower byte at pci config space 0x08 is device revision and is read-only. 1.5 device internal register sets the device configuration registers and the two individual uart configuration registers of the v252 occupy 2k of pci bus memory address space. these add resses are offset onto the basic memory address, a value loaded into the memory base address register (bar ) in the pci local bus configuration register set. the uart configuration registers are mapped into 4 addr ess blocks where each uart channel occupies 512 bytes memory space for its own registers that incl ude the 16550 compatible registers. the device configuration registers are embedded inside the uart channel zero?s address space between 0x0080 to 0x0093. all these registers can be accessed in 8, 16, 24 or 32 bits width depending on the starting address given by the host at beginning of the bus cycle. transmit and receive data may be loaded or unloaded in 8, 16, 24 or 32 bits format in special locations given in the table 5 below. every time a read or write operation is made to the transmit or receive register, its fifo data pointer is automatically bumped to the next sequential data location either in byte, word or dword. one special case applies to the receive data unloading when reading the receive data together with its lsr register cont ent. the host must read them in 16 or 32 bits format in order to maintain integrity of the data byte with its associated error flags. these special registers are further discussed in ?section 3.1, fifo data loading and unl oading in 32-bit format? on page 25 . t able 4: eeprom a ddress d efinitions eeprom m emory a ddress eeprom d ata [d15:d0] v252? s pci c onfiguration s pace a ddress (word o ffset ) d efault v alues 0x00 vendor id 0x00 0x13a8 0x01 device id 0x02 0x0252 0x02 class code * 0x08 0x0200 0x03 class code (continued) 0x0a 0x0700 0x04 subsystem vendor id 0x2c 0x0000 0x05 subsystem id 0x2e 0x0000 0x06 special register (lower word) 0x48 0x0000 0x07 special register (upper word) 0x4a 0x0000 XR17V252 13 rev. 1.0.1 66 mhz pci bus dual uart with power management support t able 5: XR17V252 uart and d evice c onfiguration r egisters o ffset a ddress m emory s pace r ead /w rite d ata w idth c omment 0x000 - 0x00f uart channel 0 regs ( table 13 & table 14 ) 8/16/24/32 first 8 regs are 16550 compatible 0x010 - 0x07f reserved 0x080 - 0x093 device configura - tion registers ( table 6 ) 8/16/24/32 0x094 - 0x0ff reserved 0x100 uart 0 ? read fifo read-only 8/16/24/32 64 bytes of rx fifo data 0x100 uart 0 ? write fifo write-only 8/16/24/32 64 bytes of tx fifo data 0x140 - 0x17f reserved 0x180 - 0x1ff uart 0 ? read fifo with errors read-only 16/32 64 bytes of rx fifo data + lsr 0x200 - 0x20f uart channel 1 regs ( table 13 & table 14 ) 8/16//24/32 first 8 regs are 16550 compatible 0x210 - 0x2ff reserved d 0x300 uart 1 ? read fifo read-only 8/16/24/32 64 bytes of rx fifo data 0x300 uart 1 ? write fifo write-only 8/16/24/32 64 bytes of tx fifo data 0x340 - 0x37f reserved 0x380 - 0x3ff uart 1 ? read fifo with errors read-only 16/32 64 bytes of rx fifo data + lsr XR17V252 14 66 mhz pci bus dual uart with power management support rev. 1.0.1 1.6 device configuration registers the device configuration registers provide easy progra mming of general operating parameters to the v252 and for monitoring the status of various functions. th ese registers control or report on all 4 channel uarts functions that include interrupt control and status, 16-bit general purpose timer control and status, multipurpose inputs/outputs control and status, sleep mode control, soft -reset control, and device identification and revision, and others. tables 6 and 7 below show these registers in byte and dword alignment. each of these registers is described in detail in the following paragraphs. t able 6: d evice c onfiguration r egisters shown in byte alignment a ddress [a7:a0] r egister r ead /w rite c omment reset state ox080 int0 [7:0] read-only interrupt [7:0] bits [7:0] = 0x00 ox081 int1 [15:8] read-only bits [7:0] = 0x00 ox082 int2 [23:16] read-only bits [7:0] = 0x00 ox083 int3 [31:24] read-only bits [7:0] = 0x00 ox084 timercntl read/write timer control bits [7:0] = 0x00 ox085 timer reserved bits [7:0] = 0x00 ox086 timerlsb read/write timer lsb bits [7:0]= 0x00 ox087 timermsb read/write timer msb bits [7:0]= 0x00 ox088 8xmode read/write bits [7:0] = 0x00 ox089 rega reserved bits [7:0] = 0x00 ox08a reset write-only self clear bits after executing reset bits [7:0] = 0x00 ox08b sleep read/write sleep mode bits [7:0]= 0x00 ox08c drev read-only device revision bits [7:0] = current rev. ox08d dvid read-only device identification bits [7:0] = 0x38 ox08e regb write-only bits [7:0] = 0x00 ox08f mpioint read/write mpio interrupt mask bits [7:0] = 0x00 ox090 mpiolvl read/write mpio level control bits [7:0] = 0x00 ox091 mpio3t read/write mpio output control bits [7:0] = 0x00 ox092 mpioinv read/write mpio input polarity select bits [7:0] = 0x00 ox093 mpiosel read/write mpio select bits [7:0] = 0xff XR17V252 15 rev. 1.0.1 66 mhz pci bus dual uart with power management support 1.6.1 the global interrupt register the XR17V252 has a 32-bit wide register [int0, int1, in t2 and int3] to provide interrupt information and supports two interrupt schemes. the first scheme uses bi ts 0 to 1 of an 8-bit indicator (int0) representing channels 0 to 1 of the XR17V252, respectively. this pe rmits the interrupt routine to quickly vector and serve that uart channel and determine the source(s) in each i ndividual routines. int0 bit-0 represents the interrupt status for uart channel 0 when its transmitter, receiver , line status, or modem port status requires service. int0 bit-1 provides interrupt status for channel 1 and bits 2 to 7 are reserved and remain at a logic 0. the second scheme provides detail about the source of the interrupts for each uart c hannel. all the interrupts are encoded into a 3-bit code per channel. this 3-bit co de represents 7 interrupts corresponding to individual uart?s transmitter, receiver, line status, modem port stat us. int1 and int2 registers provide the 6-bit interrupt status for both channels. bits 8, 9 and 10 represents channel 0 and bits 11,12 and 13 represents channel 1. bits 14 to 31 are reserved and remain at logic zero. both channels interrupt status are available with a single dword read operation. this feature allows the host to quickly vector and serve the interrupts, reducing service interval, hence, reducing host bandwidth requirements. figure 5 shows the 4-byte interrupt register and its make up. a special interrupt condition is generated by the v252 when it wakes up from sleep mode. this special interrupt is cleared by reading the int0 register. if t here are not any other interrupts pending, the value read from int0 would be 0x00. int0 [7:0] channel interrupt indicator each bit gives an indication of the channel that has requ ested for service. bit-0 repr esents channel 0 and bit-1 indicates channel 1. logic 1 indicates that a channel has requested for service. bits 2 to 7 are reserved and remain at logic zero the interrupt bit clears after readi ng the appropriate register of the interrupting channel register, see interrupt clearing section. t able 7: d evice c onfiguration r egisters shown in dword alignment a ddress r egister b yte 3 [31:24] b yte 2 [23:16] b yte 1 [15:8] b yte 0 [7:0] 0x080 - 083 interrupt (read-only) int3 int2[ int1 int0 0x084-087 timer (read/write) timermsb timerlsb timer (reserved) timercntl 0x088-08b ancillary1 (read/write) sleep reset rega 8xmode 0x08c-08f ancillary2 (read-only) mpioint regb dvid drev 0x090-093 mpio (read/write) mpiosel mpioinv mpio3t mpiolvl global interrupt register (dword) [default 0x00-00-00-00] int3 [31:24] int2 [23:16] int1 [15:8] int0 [7:0] the int0 register provides status for each channel int0 register individual uart channel interrupt status rsvd rsvd rsvd ch-1 ch-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 rsvd rsvd rsvd XR17V252 16 66 mhz pci bus dual uart with power management support rev. 1.0.1 registers int3, int2 and int1 [32:8] twenty four bit encoded interrupt indicator. each channel?s interrupt is encoded into 3 bits for receive, transmit, and status. bit [10:8] repres ent channel 0 and channel 1 with bits [13: 11]. the 3 bit encoding and their priority order are shown below in table 8 . the timer and mpio interrupts are fo r the device and therefore they exist within channel 0 (bits [10:8]) only.. f igure 5. t he g lobal i nterrupt r egister , int0, int1, int2 and int3 t able 8: uart c hannel [1:0] i nterrupt s ource e ncoding p riority b it [ n +2] b it [ n +1] b it [ n ] i nterrupt s ource ( s ) x 0 0 0 none or wake-up indicator 1 0 0 1 rxrdy and rx line status (logic or of lsr[4:1]) 2 0 1 0 rxrdy time-out 3 0 1 1 txrdy, thr or tsr ( auto rs485 mode) empty 4 1 0 0 msr, rts/cts or dtr/dsr delta or xoff /xon det. or special char. detected 5 1 0 1 reserved. 6 1 1 0 mpio pin(s). available only in channel 0, reserved in channel 1. 7 1 1 1 timer time-out. available only in channel 0, reserved channel 1. t able 9: uart c hannel [1:0] i nterrupt c learing rxrdy is cleared by reading data in the rx fi fo until it falls below the trigger level. rxrdy time-out is cleared by readi ng data until the rx fifo is empty. rx line status interrupt clears after reading the lsr register. txrdy interrupt clears after reading isr register that is in the uart channel register set. modem status register interrupt clears after reading msr register that is in the uart channel register set. rts/cts or dtr/dsr delta interrupt clears after reading ms r register that is in the uart channel register set. xoff/xon interrupt clears after reading the isr regi ster that is in the uart channel register set. special character detect interrupt is cleared by a read to isr or after the next character is received. timer time-out interru pt clears after reading the timercntl register th at is in the device configuration register set. mpio interrupt clears after reading th e mpiolvl register that is in the device configuration register set. rsvd rsvd channel-1 channel-0 int2 register int1 register int3 register int0 register interrupt registers, int0, int1, int2 and int3 bit-0 bit-1 bit-2 bit-3 bit-7 bit-4 bit-5 bit-6 rsvd rsvd ch-1 ch-0 bit n+1 bit n+2 bit n bit n+1 bit n+2 bit n bit n+1 bit n+2 bit n bit n+1 bit n+2 bit n bit n+1 bit n+2 bit n bit n+1 bit n+2 bit n bit n+1 bit n+2 bit n bit n+1 bit n+2 bit n rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd XR17V252 17 rev. 1.0.1 66 mhz pci bus dual uart with power management support 1.6.2 general purpose 16-bit timer/counter [timermsb, ti melsb, timer, timecntl] ( default 0 x xx-xx-00-00) a 16-bit down-count timer for general purpose timer or counter. its clock source may be selected from internal crystal oscillator or ex ternally on pin tmrck. the timer can be set to be a single-shot fo r a one-time event or re-triggerable for a periodic signal. an interrupt may be ge nerated when the timer times out and will show up as a channel 0 interrupt (see table 8 ). it is controlled through 4 configuration registers [timercntl, timer, timelsb, timermsb]. the timercntl re gister provides the timer commands such as start/stop, as shown in table 10 below. the time-out output of the timer can also be optionally routed to the mpio[0] pin. the block diagram of the timer/counter circuit is shown below: timermsb [31:24] and timerlsb [23:16] the concatentaion of the 8-bit registers timermsb an d timerlsb forms a 16-bit value which decides the time-out period of the timer, per the following equation: timer output frequency = timer input clock / 16-bit timer value the least-significant bit of the timer is being bit [0] of the timerlsb with most-signi ficant-bit being bit [7] in timermsb. notice that these register s do not hold the current counter value when read. default value is zero (timer disabled) upon powerup and reset. the ?reset timer? command does not have any effect on this register. timer [15:8] reserved f igure 6. t imer /c ounter circuit . timer interrupt timer output mpiolvl[0] 0 1 0 1 timer interrupt no interrupt mpio[0] tmrck osc. clock timercntl commands 16-bit timer/counter start/stop timer interrupt enable/ disable single shot/re-triggerable timermsb and timerlsb (16-bit value) 0 1 clock select route/de-route to mpio[0] timermsb register bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 bit-9 bit-8 timerlsb register bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 16-bit timer/counter programmable registers XR17V252 18 66 mhz pci bus dual uart with power management support rev. 1.0.1 timercntl [7:0] register the bits [3:0] of this register are used to issue comm ands. the commands are self-clearing, so reading this register does not show the last written command. reading this register returns a value of 0x01 when the timer interrupt is enabled and there is a pending timer interrup t. it returns a value of 0x00 at all other times. the default settings of the timer, upon power-up, a hardware reset or upon the issue of a ?timer reset? command are: timer interrupt disabled re-triggerable mode selected internal crystal oscillator out puts selcted as clock source timer output not routed to mpio[0] timer stopped timer operation the following paragraphs describe the op eration of the 16-bit timer/counter. the following conventions will be used in this discussion: ?n? is the 16-bit value programmed in the timer m sb, lsb registers p +q = n, where ?p? and ?q? are approximately half of ?n?. if n is even, p = q = n/2. if n is odd, p = (n ? 1)/2 and q = (n + 1)/2. ?n? can take any value from 0x0002 to 0xffff. timer operation in one-shot mode: in the one-shot mode, the timer output will stay high wh en started (default state) and will continue to stay high until it times out (reaches the te rminal count of ?n? clocks), at whic h time it will become low and stay low. if the timer is re-started befor e the timer times out, the counter is reset and the timer will wait for another time-out period before setting its output low (see figure 7 ). if the timer times out, re-starting the timer does not have any ef fect and a ?stop timer? co mmand needs to be issued fi rst which will set the timer output to its default high state. the timer must be programmed while it is stopped since the following operations are blocked after the timer has been started: any write to timer msb, lsb registers issue of any command other than ?start timer?, ?stop timer? and ?reset timer? t able 10: timer control r egisters timercntl [7:4] reserved timercntl [3:0] these bits are used to invoke a series of comm ands that control the func tion of the timer/counter. the commands 1100 to 1111 are reserved. 0001: enable timer interrupt 0010: disable timer interrupt 0011: select one-shot mode 0100: select re-triggerable mode 0101: select internal crystal oscillat or output as clock input for the timer 0110: select external clock input through the tmrck pin for the timer 0111: route timer output to mpio[0] pin 1000: de-route timer output from mpio[0] 1001: start timer 1010: stop timer 1011: reset timer XR17V252 19 rev. 1.0.1 66 mhz pci bus dual uart with power management support timer operation in re-triggerable mode: in the re-triggerable mode, when the timer is started, the timer output will stay high until it reaches half of the terminal count n (= p clocks) and toggle low and stay low for a similar amount of time (q clocks). the above step will keep repeating until the timer is st opped at which time the output will become high (default state). see figure 7 . also, after the timer is started, re-starting the timer does not have any effect in re- triggerable mode. the timer must be programmed while it is stopped since the following operations are blocked when the timer is running: any write to timer msb, lsb registers issue of any command other than ?stop timer? and ?reset timer? (?start timer? is not allowed) routing the timer output to mpio[0] pin: mpio[0] pin is by default (on power up or reset, for ex ample) an input. however, whenever the timer output is routed to mpio[0] pin, mpio[0] will be automatica lly selected as an output mpio[0] will become high (the default state of timer output) all mpio control registers (mpiolvl , mpiosel etc) lose control over mpio[0] and get the control back only when the timer output is de-routed from mpio[0]. timer interrupt in the one-shot mode, the timer will i ssue an interrupt upon timing out whic h is ?n? clocks after the timer is started. in the re-triggerab le mode, the time r will keep issuing an interrupt ever y ?n? clocks which is on every rising edge of the timer output. th e timer interrupt can be cleared by reading the timercntl register or when a timer reset command is issued which brings th e timer back to its default settings. the timercntl will read a value of 0x01 when the timer interrupt is enabled and there is a pending in terrupt. it reads a value of 0x00 at all other times. stopping the timer does no t clear the interrupt and neither does subsequent re- starting. f igure 7. t imer o utput in o ne -s hot and r e - triggerable m odes timer output in re-triggerable mode timer output in one-shot mode after 'p' clocks start timer command issued start timer command issued 'n' clocks stop timer command issued start timer commands issued: less than 'n' clocks between successive commands < 'n' clocks after 'p' clocks after 'p' clocks after 'p' clocks after 'p' clocks after 'q' clocks after 'q' clocks after 'q' clocks after 'q' clocks < 'n' clocks XR17V252 20 66 mhz pci bus dual uart with power management support rev. 1.0.1 1.6.3 8xmode [7:0] (default 0x00) each bit selects 8x or 16x sampling rate for that uart channel, bit-0 is channel 0. logic 0 (default) selects normal 16x sampling with lo gic one selects 8x sampling rate. transm it and receive data rates will double by selecting 8x. 1.6.4 rega [15:8] reserved 1.6.5 reset [23:16] - (default 0x00) bits 0 to 1 of the reset re gister [reset] provides the software with the ability to reset t he uart(s) when there is a need. each bit is self-resetting after it is written a logic 1 to perform a reset to that channel. all registers in that channel will be reset to the default condition, see table 21 for details. bit-0 =1 resets uart channel 0 while bit-1=1 resets channel 1. 1.6.6 sleep [31:24] (default 0x00) f igure 8. i nterrupt o utput ( active low) in o ne -s hot and r e - triggerable m odes one-shot mode timer started timer timed out timercntl read re-triggerable mode timer timed out timercntl read timer timed out rsvd rsvd rsvd rsvd rsvd rsvd ch-1 ch-0 8xmode register individual uart channel 8x clock mode enable bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 rsvd rsvd rsvd rsvd rsvd rsvd ch-1 ch-0 reset register individual uart channel reset enable bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 sleep register individual uart channel sleep enable bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 rsvd rsvd rsvd ch-1 ch-0 rsvd rsvd rsvd XR17V252 21 rev. 1.0.1 66 mhz pci bus dual uart with power management support the 8-bit sleep register enables each uart separately to enter sleep mode. sleep mode reduces power consumption when the system needs to put the uart(s) to idle. the uart enters sleep mode when the following conditions are satisfied after the sleep mode is enabled (low (default) is to disable and logic high is to enable sleep mode): there is no pending interrupt rx pin is idling at a high in normal mode or a low in infrared mode the modem inputs (cts#, dsr#, cd# and ri#) are stea dy at either high or low (msr bits [3:0] = 0000) when both uart channels are put to sl eep, the on-chip oscillato r shuts off to further conserve power. in this case, the v252 is awakened by any of the following events occurring at any of the 2 uart channels: a receive data start bit transition (high to low in no rmal mode or from low to high in infrared mode) a data byte is loaded into the transmitter a change of logic state on any of the modem inputs, i. e. any of the delta bits (msr bits[7:4]) is set the v252 is ready after 32 crystal clocks to ensure full functionality. theref ore, if the v252 is awakened by a receive data start bit transition, that character (a nd the subsequent few characters) may not be received correctly. also, a special inte rrupt is generate d with an indication of no pendi ng interrupt. the v252 will return to sleep mode automatic ally after all interrupting cond itions have been serv iced and cleared. it will stay in the sleep mode of operation unt il it is disabled by resett ing the sleep register bits. 1.6.7 device identification and revision there are two internal registers that provide device iden tification and revision, dvid and drev registers. the 8-bit content in the dvid register provides device ident ification. a return value of 0x42 from this register indicates the device is a XR17V252. the drev register retu rns an 8-bit value of 0x01 for revision a with 0x02 equals to revision b and so on. this information is very useful to the software driver for identifying which device it is communicating with and to keep up with revision changes. dvid [15:8] device identification for the type of uart . the device id of the XR17V252 is 0x42. drev [7:0] revision number of the XR17V252. a 0x01 represents "revision-a" with 0x02 for rev-b and so on. regb [23:16] (default 0x00) regb register provides a control for simultaneous write to both uarts configuration register or individually. this is very useful for dev ice initialization in the power up and rese t routines. also, the register provides a facility to interface to the non-volat ile memory device such as a 93c46 eeprom. in embedd ed applications, the user can use this facility to store propriet ary data in an external eeprom. 1.6.8 regb register regb[16](read/write) low (default) write to each uart configuration registers individually. high enables simultaneous write to both uarts configuration register. regb[19:17] reserved regb[20] (write-only) control the eeck, clock, output (pin 116) on the eeprom interface. regb[21] (write-only) control the eecs, chips select, output (pin 115) to the eeprom device. regb[22] (write-only) eedi (pin 114) data input. writ e data to the eeprom device. regb[23] (read-only) eedo (pin 113) data output. read data from the eeprom device. XR17V252 22 66 mhz pci bus dual uart with power management support rev. 1.0.1 1.6.9 multi-purpose inputs and outputs the v252 provides 8 multi-purpose inputs/outputs mpio[7:0] for general use. each pin can be programmed to be an input or output function. the input logic state can be set for normal or inverted level, and optionally set to generate an interrupt. the outputs can be set to be norm al high or low state, or 3-state. their functions and definitions are programmed through 5 registers: mpioint, mpiolvl, mpio3t, mpioinv and mpiosel. if all 8 pins are set for inputs, all 8 interrupts would be or?ed together. the or?ed interrupt is reported in the channel 0 uart interrupt status, see interrupt status register. the pins may also be programmed to be outputs and to the 3-state condition for signal sharing. the mpio[0] pin can be programmed to show the timer output. when it is programmed to be the timer output, all the above 5 registers lose control over the mpio[0] pin. for details on timer output, please see ?section 1.6.2, general purpose 16 -bit timer/counter [timermsb, timelsb, timer, timecntl] (def ault 0xxx-xx-00-00)? on page 17 . 1.6.10 mpio register bit [7] represents mpio7 pin and bit [0] represents mpio 0 pin. there are 5 registers that select, control and monitor the 8 multipurpose inputs and outputs. figure 9 shows the internal circuitry. f igure 9. m ultipurpose input / output internal circuit mpio pin [7:0] mpiolvl [7:0] read input level mpioint [7:0] rising edge detection int or and and 1 0 mpiosel [7:0] (select input=1, output=0 ) mpio3t [7:0] (3-state enable =1) mpiolvl [7:0] (output level) mpioinv [7:0] (input inversion enable =1) mpiockt XR17V252 23 rev. 1.0.1 66 mhz pci bus dual uart with power management support mpioint [7:0] (default 0x00) enable multipurpose input pin interrupt. if the pin is selected by mpiosel as input then bit [0] enables input pin 0 for interrupt, and bit [7] enables input pin 7. no interrupt is enable if the pin is selected to be an output. the interrupt is edge sensing and determined by mpioin v and mpiolvl registers. the mpio interrupt clears after a read to register mpiolvl. the combination of mpiolvl and mpioinv determines the interrupt being active low or active high, it?s level trigger. logic lo w (default) disables the pin?s interrupt and logic high enables it. mpiolvl [7:0] (default 0x00) output pin level control and input level status. the status of the input pin(s) is read on this register and output pins are controlled on this register. a logic 0 (default) se ts the output to low and a logic 1 sets the output pin to high. the mpio interrupt will cl ear upon reading this register. mpio3t [7:0] (default 0x00) output pin tri-state control. a logic 0 (default) sets the output to active level per register mpiobit settling, a logic 1 sets the output pin to tri-state. mpioinv [7:0] (default 0x00) input inversion control. a logic 0 (default) does not inve rt the input pin logic. a logic 1 inverts the input logic level. mpio6 mpio7 mpio5 mpio4 mpio3 mpio2 mpio1 mpio0 mpioint register multipurpose input/output interrupt enable bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 mpio6 mpio7 mpio5 mpio4 mpio3 mpio2 mpio1 mpio0 mpiolvl register multipurpose output level control bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 mpio6 mpio7 mpio5 mpio4 mpio3 mpio2 mpio1 mpio0 mpio3t register multipurpose output 3-state enable bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 mpio6 mpio7 mpio5 mpio4 mpio3 mpio2 mpio1 mpio0 mpioinv register multipurpose input signal inversion enable bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 XR17V252 24 66 mhz pci bus dual uart with power management support rev. 1.0.1 mpiosel [7:0] (default 0xff) multipurpose input/output pin select. this register defines the functions of the pins. a logic 1 (default) defines the pin for input and a logic 0 for output. 2.0 crystal oscillator / buffer the v252 includes an on-chip oscilla tor (xtal1 and xtal2). the crystal os cillator provides the system clock to the baud rate generators (brg) in each of the 2 uarts, the 16-bit general purpose timer/counter and internal logics. xtal1 is the input to the oscillator or external clock bu ffer input with xt al2 pin being the output. see the programmable baud rate generator in the uart section on page 28 for programming details. the on-chip oscillator is designed to us e an industry standard microprocessor crystal (p arallel resonant with 10-22 pf capacitance load, 100ppm) connected externally between the xtal1 and xtal2 pins (see figure 10 ). alternatively, an external clock can be connected to the xtal1 pin to clock the internal 2 baud rate generators for stan dard or custom rates. typically, th e oscillator connections are shown in figure 10 . for further reading on oscillator circuit please se e application note dan 108 on exar?s web site. f igure 10. t ypical c rystal connections mpio6 mpio7 mpio5 mpio4 mpio3 mpio2 mpio1 mpio0 mpiosel registe r multipurpose input/output selection bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 c1 22-47pf c2 22-47pf 14.7456 mhz xtal1 xtal2 r=300k to 400k XR17V252 25 rev. 1.0.1 66 mhz pci bus dual uart with power management support 3.0 transmit and receive data there are two methods to load transmit data and unload receive data from each uart channel. first, there is a transmit data register and receive data register for each uart channel as shown in table 5 set to ease programming. these registers support 8, 16 , 24 and 32 bits wide format. in the 32-bit format, it increases the data transfer rate on the pci bus. additionally, a special register location provides receive data byte with its associated error flags. this is a 16-bit or 32-bit read operation where the line status register (lsr) content in the uart channel register is paired along with the data byte. this operation fu rther facilitates data unloading with the error flags without having to read the lsr register separately. furthermore, the XR17V252 supports pci burst mode for read/write oper ation of up to 64 bytes of data. the second method is through each uart channel?s transmit holding register (thr) and receive holding register (rhr). the thr and rhr registers are 16550 comp atible so their access is limited to 8-bit format. the software driver must separately read the lsr cont ent for the associated error flags before reading the data byte. 3.1 fifo data loading and unloading in 32-bit format the XR17V252 supports pci burst read and pci burst write transactions anywhere in the mapped memory region (except reserved areas). in addition, to utilize this feature fully, th e device provides a separate memory location (apart from the individual channel?s register set) where the rx and the tx fifo can be read from/ written to, as shown in table 5 . the following is an extract from the table showing the burstable memory locations: channel 0: rx fifo : 0x100 - 0x13f (64 bytes) tx fifo : 0x100 - 0x13f (64 bytes) rx fifo + status : 0x180 - 0x1ff (64 bytes data + 64 bytes status) channel 1: rx fifo : 0x300 - 0x33f (64 bytes) tx fifo : 0x300 - 0x33f (64 bytes) rx fifo + status : 0x380 - 0x3ff (64 bytes data + 64 bytes status) XR17V252 26 66 mhz pci bus dual uart with power management support rev. 1.0.1 3.1.1 normal rx fifo data unloading at locations 0x100 (channel 0) and 0x300 (channel 1) the rx fifo data (up to the maximum 64 bytes) can be read out in a single burst 32-bit read operation (maximum 16 dword reads) at memory locations 0x100 (c hannel 0) and 0x300 (channel 1). this operation is at least 16 times faster than reading the data in 64 separate 8-bit memory reads of rhr register (0x000 for channel 0 and 0x200 for channel 1). 3.1.2 special rx fifo data unloading at locations 0x180 (channel 0) and 0x380 (channel 1) the xr17d152 also provides the same rx fifo data al ong with the lsr status information of each byte side- by-side, at locations 0x180 (channel 0) and 0x380 (channel 1). the entire rx data along with the status can be downloaded in a single pci burst read operation of 32 dword reads. the status and data bytes must be read in 16 or 32 bits format to maintain data integrity. the following tables show this clearly. r ead rx fifo, with n o e rrors b yte 3 b yte 2 b yte 1 b yte 0 read n+0 to n+3 fifo data n+3 fifo data n+2 fifo data n+1 fifo data n+0 read n+4 to n+7 fifo data n+7 fifo data n+6 fifo data n+5 fifo data n+4 etc. r ead rx fifo, with lsr e rrors b yte 3 b yte 2 b yte 1 b yte 0 read n+0 to n+1 fifo data n+1 lsr n+1 fifo data n+0 lsr n+0 read n+2 to n+3 fifo data n+3 lsr n+3 fifo data n+2 lsr n+2 etc pci bus data bit-31 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 receive data byte n+3 receive data byte n+2 receive data byte n+1 receive data byte n+0 pci bus data bit-0 channel 0 to 1 receivedata in 32-bit alignment through the configuration register address 0x0100 and 0x0300 pci bus data bit-31 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 receive data byte n+1 line status register n+1 r eceive data byte n+0 line status register n+0 pci bus data bit-0 channel 0 to 1 receive data with line status register in a 32-bit alignment through the configuration register address 0x0180 and 0x0380 XR17V252 27 rev. 1.0.1 66 mhz pci bus dual uart with power management support 3.1.3 tx fifo data loading at locations 0x100 (channel 0) and 0x300 (channel 1) the tx fifo data (up to the maximum 64 bytes) can be loaded in a single burst 32-bit write operation (maximum 16 dword writes) at memory location s 0x100 (channel 0) and 0x300 (channel 1). 3.2 fifo data loading and unloading through the uart channel registers, thr and rhr in 8-bit format the thr and rhr register address for channel 0 to channel 1 is shown in table 11 below. the thr and rhr for each channel 0 tand 1 are located sequentially at address 0x0000 and 0x0200. transmit data byte is loaded to the thr when writing to that address and receive data is unloaded from the rhr register when reading that address. both thr and rhr registers ar e 16c550 compatible in 8-bit format, so each bus operation can only write or read in bytes. w rite tx fifo b yte 3 b yte 2 b yte 1 b yte 0 write n+0 to n+3 fifo data n+3 fifo data n+2 fifo data n+1 fifo data n+0 write n+4 to n+7 fifo data n+7 fifo data n+6 fifo data n+5 fifo data n+4 etc. t able 11: t ransmit and r eceive d ata r egister in b yte format , 16c550 compatible pci bus data bit-31 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 transmit data byte n+3 transmit data byte n+2 transmit data byte n+1 transmit data byte n+0 pci bus data bit-0 channel 0 to 1 transmit data in 32-bit ali gnment through the configuration register address 0x0100 and 0x0300 thr and rhr address locations for ch0 to ch1 (16c550 compatible) ch0 0x000 write thr ch0 0x000 read rhr ch1 0x200 write thr ch1 0x200 read rhr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 XR17V252 28 66 mhz pci bus dual uart with power management support rev. 1.0.1 4.0 uart there are 2 uarts channel [1:0] in the v252. each has its own 64-byte of transmit and receive fifo, a set of 16550 compatible control and status registers, and a baud rate generator for individual channel data rate setting. eight additional registers per uart were added for the exar enhanced features. 4.1 programmable baud rate generator with fractional divisor each uart has its own baud rate generator (brg) with a prescaler for the transmitter and receiver. the prescaler is controlled by a software bit in the mcr r egister. the mcr register bit [7] sets the prescaler to divide the input crystal or external clock by 1 or 4. the output of the prescaler clocks to the brg. the brg further divides this clock by a programmable divisor between 1 and (2 16 - 0.0625) in increments of 0.0625 (1/ 16) to obtain a 16x or 8x sampling clock of the serial data rate. the sampling clock is used by the transmitter for data bit shifting and receiver for data sampling. the brg divisor (dll, dlm and dld registers) defaults to a random value upon power up. therefor e, the brg must be programmed duri ng initialization to the operating data rate. the dll and dlm registers provide the integer part of the divisor and the dld register provides the fractional part of the divisor. only the four lower bits of the dld are implemented and they are used to select a value from 0 (for setting 0000) to 0.9375 or 15/16 (for setting 1111). programming the baud rate generator registers dll, dlm and dld provides the capa bility for selecting t he operating data rate. table 12 shows the standard data rates available with a 14.7456 mhz crystal or external clock at 16x clock rate. if the pre-scaler is used (mcr bit [7] = 1), the output data rate will be 4 times less than that shown in table 12 . at 8x sampling rate, these data ra tes would double. also, when using 8x samplin g mode, please note that the bit-time will have a jitter (+/- 1/16) whenever the dld is an odd number. when using a non-standard data rate crystal or external clock, the divisor value can be calculated with the following equation(s): the closest divisor that is obtainable in the v2 52 can be calculated using the following formula: in the formulas above, please note that: trunc (n) = integer part of n. for example, trunc (5.6) = 5. round (n) = n rounded towards the cl osest integer. for example, roun d (7.3) = 7 and round (9.9) = 10. required divisor (decimal) = (xtal1 clock frequency / prescaler) / (serial data rate x 16), with 8xmode [7:0] is 0 required divisor (decimal) = (xtal1 clock frequency / prescaler / (serial data rate x 8), with 8xmode [7:0] is 1 round( (required divisor - trunc (required divisor) )*16)/16 + trunc (required divisor), where dlm = trunc( required divisor) >> 8 dll = trunc (required divisor) & 0xff dld = round ( (required divisor-trunc(required divisor) )*16) XR17V252 29 rev. 1.0.1 66 mhz pci bus dual uart with power management support f igure 11. b aud r ate g enerator t able 12: t ypical data rates with a 24 mh z crystal or external clock at 16x s ampling r equired o utput d ata r ate d ivisor for 16x clock (decimal) d ivisor o btainable in v252 dlm p rogram v alue (hex) dll p rogram v alue (hex) dld p rogram v alue (hex)) d ata e rror r ate (%) 400 3750 3750 e a6 0 0 2400 625 625 2 71 0 0 4800 312.5 312 8/16 1 38 8 0 9600 156.25 156 4/16 0 9c 4 0 10000 150 150 0 96 0 0 19200 78.125 78 2/16 0 4e 2 0 25000 60 60 0 3c 0 0 28800 52.0833 52 1/16 0 34 1 0.04 38400 39.0625 39 1/16 0 27 1 0 50000 30 30 0 1e 0 0 57600 26.0417 26 1/16 0 1a 1 0.08 75000 20 20 0 14 0 0 100000 15 15 0 f 0 0 115200 13.0208 13 0 d 0 0.16 153600 9.7656 9 12/16 0 9 c 0.16 200000 7.5 7 8/16 0 7 8 0 225000 6.6667 6 11/16 0 6 b 0.31 230400 6.5104 6 8/16 0 6 8 0.16 250000 6 6 0 6 0 0 300000 5 5 0 5 0 0 400000 3.75 3 12/16 0 3 c 0 460800 3.2552 3 4/16 0 3 4 0.16 500000 3 3 0 3 0 0 750000 2 2 0 2 0 0 921600 1.6276 1 10/16 0 1 a 0.16 1000000 1.5 1 8/16 0 1 8 0 xtal1 xtal2 crystal osc/ buffer mcr bit-7=0 (default) mcr bit-7=1 dll, dlm and dld registers prescaler divide by 1 prescaler divide by 4 16x or 8x sampling rate clock to transmitter and receiver to other channels fractional baud rate generator logic XR17V252 30 66 mhz pci bus dual uart with power management support rev. 1.0.1 4.2 automatic hardware (rts/cts or dtr/dsr) flow control operation automatic hardware or rts/dtr and cts/dsr flow control is used to prevent data overrun to the local receiver fifo and remote receiver fifo. the rts#/dtr# output pin is used to request remote unit to suspend/restart data transmission while the cts#/dsr # input pin is monitored to suspend/restart local transmitter. the auto rts/dtr and auto cts/dsr flow cont rol features are individually selected to fit specific application requirement and enabled through efr bit[6 :7] and mcr bit [2] for either rts/cts or dtr/dsr control signals. the auto rts/dtr function must be star ted by asserting rts/dtr# output pin (mcr bit [0] or bit [1] to logic 1) after it is enabled. figure 12 below explains how it works. two interrupts associated with rts/dtr and cts/dsr flow control have been added to give indication when rts/dtr# pin or cts/dsr# pin is de-asserted during operation. the rts/dtr and cts/dsr interrupts must be first enabled by efr bit [4], and then enabled individu ally by ier bits [7:6], and chosen with mcr bit [2]. automatic hardware flow contro l is selected by setting bits [7 (cts): 6 (rts)] of the efr register to logic 1. if cts# pin transitions from low to high indicating a flow control request, is r bit [5] will be set to logic 1, (if enabled via ier bit [7:6]), and the uart will suspend tx tr ansmissions as soon as t he stop bit of the character in process is shifted out. transmission is resumed after the cts# input returns to low, indicating more data may be sent. XR17V252 31 rev. 1.0.1 66 mhz pci bus dual uart with power management support f igure 12. a uto rts/dtr and cts/dsr f low c ontrol o peration the local uart (uarta) starts data transf er by asserting -rtsa# (1). rtsa# is normally connected to ctsb# (2) of remote uart (uartb). ctsb# allows its transmitter to se nd data (3). txb data arrives and fills uarta receive fifo (4). when rxa data fills up to its receive fifo trigger le vel, uarta activates its rxa data ready interrupt (5) and con - tinues to receive and put data into its fifo. if interrupt se rvice latency is long and data is not being unloaded, uarta monitors its receive data fill level to match the upper thre shold of rts delay and de-assert rtsa# (6). ctsb# follows (7) and request uartb transmitter to suspend data transfer. ua rtb stops or finishes sending the data bits in its trans - mit shift register (8). when receive fifo data in uarta is unloaded to match the lower threshold of rts delay (9), uarta re-asserts rtsa# (10), ctsb# recognizes the change (11) and restarts its transmitter and data flow again until next receive fifo trigger (12). this same event applies to the reverse direction when uarta sends data to uartb with rtsb# and ctsa# controlling the data flow. rtsa# ctsb# rxa txb transmitter receiver fifo trigger reached auto rts trigger level auto cts monitor rtsa# txb rxa fifo ctsb# remote uart uartb local uart uarta on off on suspend restart rts high threshold data starts on off on assert rts# to begin transmission 1 2 3 4 5 6 7 receive data rts low threshold 9 10 11 receiver fifo trigger reached auto rts trigger level transmitter auto cts monitor rtsb# ctsa# rxb txa inta (rxa fifo interrupt) rx fifo trigger level rx fifo trigger level 8 12 rtscts1 XR17V252 32 66 mhz pci bus dual uart with power management support rev. 1.0.1 4.3 infrared mode each uart in the v252 includes the infrared encoder and decoder compatible to the irda (infrared data association) version 1.0. the input pin enir convenient ly activates both uart channels to start up in the infrared mode. this global control pin enables the mcr bit [6] function in every uart channel register. after power up or a reset, the software can overwrite mcr bit [6 ] if so desired. enir and mcr bit [6] also disable its receiver while the transmitter is sending data. this prev ents the echoed data from going to the receiver. the global activation enir pin prevents the infrared emitter from turning on and drawing large amount of current while the system is starting up. when the infrared featur e is enabled, the transmit da ta outputs, tx[7:0], would idle at logic 0 level. likewise, the rx [7:0 ] inputs assume an idle level of logic 0. the infrared encoder sends out a 3/16 of a bit wide pulse for each ?low? bit in the transmit data stream. this signal encoding reduces the on-time of the infrared led, hence reduces the power consumption. see figure 13 below. the infrared decoder receives the input pulse from th e infrared sensing diode on rx pin. each time the decoder senses a light pulse, it returns a low to the da ta bit stream. the rx input signal may be inverted prior delivered to the input of the decoder vi a internal register setting. this op tion supports active low instead of normal active high pulse from so me infrared modules on the market. f igure 13. i nfrared t ransmit d ata e ncoding and r eceive d ata d ecoding character data bits start stop 0000 0 11 111 bit time 1/16 clock delay irdecoder - rx data receive ir pulse (rx pin) character data bits start stop 0000 0 11 111 tx data transmit ir pulse (tx pin) bit time 1/2 bit time 3/16 bit time irencoder-1 XR17V252 33 rev. 1.0.1 66 mhz pci bus dual uart with power management support 4.4 internal loopback each uart channel provides an inte rnal loopback capabilit y for system di agnostic. the in ternal loopback mode is enabled by setting mcr register bit [4] to logic 1. all regular uart functions operate normally. figure 14 shows how the modem port signals are re-configured. transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to receive the same data that it was sending. the tx pin is held at high or mark co ndition while rts# and dtr# are de-asserted, and cts#, dsr# cd# and ri# inputs are ignored. 4.5 uart channel configuration re gisters and address decoding the 2 sets of uart configuration registers are deco ded using address lines a9 to a11 as shown below. address lines a0 to a3 select the 16 registers in each channel. the first 8 registers are 16550 compatible with exar enhanced feature registers lo cated on the upp er 8 addresses. f igure 14. i nternal l oop b ack a11 a10 a9 uart c hannel s election 0 0 0 0 0 0 1 1 tx [1:0] rx [1:0] modem / general purpose control logic internal bus lines and control signals rts# [1:0] mcr bit-4=1 vcc vcc vcc transmit shift register receive shift register cts# [1:0] dtr# [1:0] dsr# [1:0] ri# [1:0] cd# [1:0] op1# op2# rts# cts# dtr# dsr# ri# cd# XR17V252 34 66 mhz pci bus dual uart with power management support rev. 1.0.1 t able 13: uart channel configuration registers. a ddress r egister r ead /w rite c omments a3 a2 a1 a0 16550 c ompatible 0 0 0 0 rhr - receive holding reg thr - transmit holding register read-only write-only lcr[7] = 0 0 0 0 0 dll - divisor lsb read/write lcr[7] = 1 0 0 0 1 dlm - divisor msb read/write lcr[7] = 1 0 0 1 0 dld - divisor fractional part read/write lcr[7] = 1 0 0 0 1 ier - interrupt enable reg read/write lcr[7] = 0 0 0 1 0 isr - interrupt status reg fcr - fifo control reg read-only write-only lcr[7] = 0 0 0 1 1 lcr - line control reg read/write 0 1 0 0 mcr - modem control reg read/write 0 1 0 1 lsr - line status reg reserved read-only write-only 0 1 1 0 msr - modem status reg - auto rs485 delay read-only write-only 0 1 1 1 spr - scratch pad reg read/write e nhanced r egister 1 0 0 0 fctr read/write 1 0 0 1 efr - enhanced function reg read/write 1 0 1 0 txcnt - transmit fifo level counter txtrg - transmit fifo trigger level read-only write-only 1 0 1 1 rxcnt - receive fifo level counter rxtrg - receive fifo trigger level read-only write-only 1 1 0 0 xoff-1 - xoff character 1 xchar write-only read-only xon,xoff rcvd. flags 1 1 0 1 xoff-2 - xoff character 2 reserved write-only read-only 1 1 1 0 xon-1 - xon character 1 reserved write-only read-only 1 1 1 1 xon-2 - xon character 2 reserved write-only read-only XR17V252 35 rev. 1.0.1 66 mhz pci bus dual uart with power management support t able 14: uart channel configurati on registers description. s haded bits are enabled by efr b it -4. a ddress a3-a0 r eg n ame r ead / w rite b it [7] b it [6] b it [5] b it [4] b it [3] b it [2] b it [1] b it [0] c omment 0 0 0 0 rhr r bit [7] bit [6] bit [5] bit [4] bit [3] bit [2] bit [1] bit [0] lcr[7]=0 0 0 0 0 thr w bit [7] bit [6] bit [5] bit [4] bit [3] bit [2] bit [1] bit [0] lcr[7]=0 0 0 0 0 dll r/w bit [7] bit [6] bit [5] bit [4] bit [3] bit [2] bit [1] bit [0] lcr[7]=1 0 0 0 1 dlm r/w bit [7] bit [6] bit [5] bit [4] bit [3] bit [2] bit [1] bit [0] lcr[7]=1 0 0 1 0 dld r/w 0 0 0 0 bit [3] bit [2] bit [1] bit [0] lcr[7]=1 0 0 0 1 ier r/w 0/ 0/ 0/ 0 modem status int. enable rx line status int. enable tx empty int. enable rx data int. enable lcr[7]=0 cts/ dsr# int. enable rts/ dtr# int. enable xon/ xoff/sp. char. int. enable 0 0 1 0 isr r fifos enable fifos enable 0/ 0/ int source bit [3] int source bit [2] int source bit [1] int source bit [0] lcr[7]=0 delta - flow cntl xoff/spe - cial char 0 0 1 0 fcr w rx fifo trigger r x f i f o trigger 0/ 0/ dma mode tx fifo reset rx fifo reset fifos enable lcr[7]=0 tx fifo trigger tx fifo trigger 0 0 1 1 lcr r/w divisor enable set tx break set par - ity even par - ity parity enable stop bits word length bit [1] word length bit [0] 0 1 0 0 mcr r/w 0/ 0/ 0/ internal loopback enable (op2) 1 (op1) 1 rts# pin con - trol dtr# pin con - trol brg pres - caler ir enable xonany tx char immedi - ate rts/ dtr flow sel 0 1 0 1 lsr r/w rx fifo e rror tsr empty thr empty rx break rx framing error rx par - ity error rx overrun rx data ready 0 1 1 0 msr r cd ri dsr cts delta cd# delta ri# delta dsr# delta cts# msr w rs485 dly-3 rs485 dly-2 rs485 dly-1 rs485 dly-0 disable tx disable rx 0 1 1 1 spr r/w bit [7] bit [6] bit [5] bit [4] bit [3] bit [2] bit [1] bit [0] user data 1 0 0 0 fctr r/w trg ta b l e bit [1] trg ta b l e bit [0] auto rs485 enable invert ir rx input rts/ dtr hyst bit [3] rts/ dtr hyst bit [2] rts/ dtr hyst bit [1] rts/ dtr hyst bit [0] XR17V252 36 66 mhz pci bus dual uart with power management support rev. 1.0.1 n ote : mcr bits [3:2] (op1 and op2 outputs) are not avai lable in the XR17V252. they are present for 16c550 compatibility during internal loopback, see figure 14 . 4.6 transmitter the transmitter section comprises of a 64 bytes of fifo , a byte-wide transmit holding register (thr) and an 8-bit transmit shift register (tsr). thr receives a dat a byte from the host (non-fifo mode) or a data byte from the fifo when the fifo is enabled by fcr bit [0]. tsr shifts out every data bit with the 16x or 8x internal clock. a bit time is 16 or 8 clock periods. th e transmitter sends the start bit followed by the number of data bits, inserts the proper parity bit if enable, and adds the stop bit(s). the st atus of the thr and tsr are reported in the line status register (lsr bit [6:5]). 4.6.1 transmit holdin g register (thr) the transmit holding register is an 8-bit register pr oviding a data interface to the host processor. the host writes transmit data byte to the thr to be converted in to a serial data stream including start-bit, data bits, parity-bit and stop-bit(s). the least-sign ificant-bit (bit [0]) becomes first data bit to go out. the thr is also the input register to the transmit fifo of 64 bytes when fifo operation is enabled by fcr bit[0]. a thr empty interrupt can be generated when it is enabled in ier bit [1]. 4.6.2 transmitter operation in non-fifo mode the host loads transmit data to thr one character at a time. the thr empty flag (lsr bit [5]) is set when the data byte is transferred to tsr. thr flag can generate a transmit empty interrupt (i sr bit [1]) when it is enabled by ier bit [1]. the tsr flag (lsr bit [6 ]) is set when tsr beco mes completely empty. 1 0 0 1 efr r/w auto cts/ dsr enable auto rts/ dtr enable special char select enable ier [7:5], isr [5:4], fcr[5:4], mcr[7:5,2] msr[7:4] soft - ware flow cntl bit [3] soft - ware flow cntl bit [2] soft - ware flow cntl bit [1] soft - ware flow cntl bit [0] 1 0 1 0 txcnt r bit [7] bit [6] bit [5] bit [4] bit [3] bit [2] bit [1] bit [0] 1 0 1 0 txtrg w bit [7] bit [6] bit [5] bit [4] bit [3] bit [2] bit [1] bit [0] 1 0 1 1 rxcnt r bit [7] bit [6] bit [5] bit [4] bit [3] bit [2] bit [1] bit [0] 1 0 1 1 rxtrg w bit [7] bit [6] bit [5] bit [4] bit [3] bit [2] bit [1] bit [0] 1 1 0 0 xchar r 0 0 0 0 tx xon indicator tx xoff indicator xon det. indicator xoff det. indicator self clear after read 1 1 0 0 xoff1 w bit [7] bit [6] bit [5] bit [4] bit [3] bit-2 bit [1] bit [0] 1 1 0 1 xoff2 w bit [7] bit [6] bit [5] bit [4] bit [3] bit-2 bit [1] bit [0] 1 1 1 0 xon1 w bit [7] bit [6] bit [5] bit [4] bit [3] bit-2 bit [1] bit [0] 1 1 1 1 xon2 w bit [7] bit [6] bit [5] bit [4] bit [3] bit-2 bit [1] bit [0] t able 14: uart channel configurati on registers description. s haded bits are enabled by efr b it -4. a ddress a3-a0 r eg n ame r ead / w rite b it [7] b it [6] b it [5] b it [4] b it [3] b it [2] b it [1] b it [0] c omment XR17V252 37 rev. 1.0.1 66 mhz pci bus dual uart with power management support 4.6.3 transmitter operation in fifo mode the host may fill the transmit fifo with up to 64 bytes of transmit data. the thr empty flag (lsr bit [5]) is set whenever the fifo is empty. the thr empty flag can ge nerate a transmit empty inte rrupt (isr bit [1]) when the amount of data in the fifo falls below its programm ed trigger level (see txtrg register). the transmit empty interrupt is enabled by ier bit [1]. the tsr fl ag (lsr bit [6]) is set when tsr becomes completely empty. furthermore, with the rs485 half-duplex direction control enabled (fctr bit [5]=1) the source of the transmit empty interrupt changes to tsr empty instead of thr empty. this is to ensure the rts# output is not changed until the last stop bit of the last character is shifted out. 4.6.4 auto rs485 operation the auto rs485 half-duplex direction control changes the behavior of the transmitter when enabled by fctr bit [5]. it de-asserts rts# or dtr# after a specified delay indicated in msr[7:4] following the last stop bit of the last character that has been transmitted. this helps in turning around the transceiver to receive the remote station?s response. the delay optimizes the time needed fo r the last transmission to reach the farthest station on a long cable network before switching off the line driver. this delay prevents undesirable line signal disturbance that causes signal degradation. it also changes the transmitter empt y interrupt to tsr empty instead of thr empty. f igure 15. t ransmitter o peration in non -fifo m ode transmit holding register (thr) transmit shift register (tsr) data byte l s b m s b thr interrupt (isr bit-1) enabled by ier bit-1 txnofifo1 16x or 8x clock (8xmode register) XR17V252 38 66 mhz pci bus dual uart with power management support rev. 1.0.1 4.7 receiver the receiver section contains an 8-bit receive shift r egister (rsr) and receive holding register (rhr). the rsr uses the 16x or 8x clock for timing. it verifies an d validates every bit on the incoming character in the middle of each data bit. on the fa lling edge of a start or false start bit, an internal receiver counter starts counting at the 16x or 8x clock rate. after 8 or 4 clo cks the start bit period should be at the center of the start bit. at this time the start bit is sampled and if it is st ill a logic 0 it is validated. ev aluating the start bit in this manner prevents the receiver from assembling a false char acter. the rest of the data bits and stop bits are sampled and validated in this same manner to prevent false framing. if there were any error(s), they are reported in the lsr register bits [4:1]. upon unload ing the receive data byte fr om rhr, the receive fifo pointer is bumped and the error flags are immediately up dated to reflect the status of the data byte in rhr register. rhr can generate a receive data ready interrupt upon receiving a character or delay until it reaches the fifo trigger level. furthermore, data delivery to th e host is guaranteed by a re ceive data ready time-out function when receive data does not reach the receive fifo trigger level. this time-out delay is 4 word lengths as defined by lcr[1:0] plus 12 bits time. the rhr interrupt is enabled by ier bit [0]. 4.7.1 receiver operation in non-fifo mode f igure 16. t ransmitter o peration in fifo and f low c ontrol m ode f igure 17. r eceiver o peration in non -fifo m ode transmit data shift register (tsr) transmit data byte thr interrupt (isr bit-1) falls below programmed trigger level (txtrg) and then when becomes empty. fifo is enabled by fcr bit-0=1 transmit fifo (64-byte) txfifo1 16x or 8x clock (8xmode register) auto cts flow control (cts# pin) auto software flow control flow control characters (xoff1/2 and xon1/2 reg. receive data shift register (rsr) receive data byte and errors rhr interrupt (isr bit-2) receive data holding register (rhr) rxfifo1 16x or 8x clock (8xmode register) receive data characters data bit validation error flags in lsr bits 4:2 XR17V252 39 rev. 1.0.1 66 mhz pci bus dual uart with power management support 4.7.2 receiver operation with fifo 5.0 uart configuration registers 5.1 receive holding register (rhr) - read only see?receiver? on page 38. 5.2 transmit holding register (thr) - write only see?transmitter? on page 36. 5.3 baud rate generator divisors (dlm, dll and dld) the baud rate generator (brg) generates the data rate for the transmitter and receiver. the rate is programmed through registers dlm, dll and dld which are on ly accessible when lcr bit [7] is set to logic 1. refer to ?section 4.1, programmable baud rate ge nerator with fractional divisor? on page 28 for more details. 5.4 interrupt enable register (ier) - read/write the interrupt enable register (ier) masks the interrupts from receive data ready, transmit empty, line status and modem status registers. these interrupts are report ed in the interrupt status register (isr) and also encoded in int (int0-int3) register in the device configuration registers. 5.4.1 ier versus receive fifo interrupt mode operation when the receive fifo (fcr bit [0] = a logic 1) and re ceive interrupts (ier bit [0] = logic 1) are enabled, the rhr interrupts (see isr bits [4:3]) status will reflect the following: a. the receive data available interrupts are issued to the host when the fifo has reached the programmed trigger level. it will be cleared when the fifo drops below the programmed trigger level. b. fifo level will be reflected in the is r register when the fifo trigger leve l is reached. both the isr register status bit and the interrupt will be cleared when the fifo drops below the trigger level. c. the receive data ready bit (lsr bit [0]) is set as soon as a character is transferred from the shift register to the receive fifo. it is rese t when the fifo is empty. f igure 18. r eceiver o peration in fifo and f low c ontrol m ode receive data shift register (rsr) rxfifo1 16x or 8x sampling clock (8xmode reg.) error flags (64-sets) error flags in lsr bits 4:2 64 bytes by 11- bit wide fifo receive data characters fifo trigger=48 example: - fifo trigger level set at 48 bytes - rts/dtr hyasteresis set at +/-8 chars. data fills to 56 data falls to 40 data bit validation receive data fifo (64-byte) receive data receive data byte and errors rhr interrupt (isr bit-2) is programmed at fifo trigger level (rxtrg). fifo is enable by fcr bit-0=1 rts#/dtr# de-asserts when data fills above the trigger level to suspend remote transmitter. enable by efr bit-6=1, mcr bit-2. rts#/dtr# re-asserts when data falls below the trigger level to restart remote transmitter. enable by efr bit-6=1, mcr bit-2. XR17V252 40 66 mhz pci bus dual uart with power management support rev. 1.0.1 5.4.2 ier versus receive/transmit fifo polled mode operation when fcr bit [0] equals a logic 1 for fifo enable; resett ing ier bits [3:0] enables the xr16v252 in the fifo polled mode of operation. since the receiver and transmitte r have separate bits in the lsr either can be used in the polled mode by selecting respective transmit or receive control bit(s). a. lsr bit-0 indicates there is data in rhr (non-fifo mode) or rx fifo (fifo mode). b. lsr bit-1 indicates an overrun error has occurred and that data in the fifo may not be valid. c. lsr bit 2-4 provides the type of receive data erro rs encountered for the data byte in rhr, if any. d. lsr bit-5 indicates thr (non-fifo mode) or tx fifo (fifo mode) is empty. e. lsr bit-6 indicates when both the transmit fifo and tsr are empty. f. lsr bit-7 indicates a data error in at least one character in the rx fifo. ier[7]: cts# input interrupt enable (requires efr bit [4]=1) ? logic 0 = disable the cts# interrupt (default). ? logic 1 = enable the cts# interrupt. the uart issues an interrupt when cts# pin makes a transition from low to high. ier[6]: rts# output interrupt enable (requires efr bit [4]=1) ? logic 0 = disable the rts# interrupt (default). ? logic 1 = enable the rts# interrupt. the uart issues an interrupt when rts# pin makes a transition from low to high. ier[5]: xoff interrupt enable (requires efr bit [4]=1) ? logic 0 = disable the software flow cont rol, receive xoff interrupt (default). ? logic 1 = enable the software flow control, receive xo ff interrupt. see software flow control section for details. ier[4]: reserved . ier[3]: modem status interrupt enable the modem status register interrupt is issued whenever any of the delta bits of the msr register (bits [3:0]) is set. ? logic 0 = disable the modem status register interrupt (default). ? logic 1 = enable the modem status register interrupt. ier[2]: receive line status interrupt enable an overrun error, framing error, pari ty error or detection of a break character will resu lt in an lsr interrupt. the v252 will issue an lsr interrupt imm ediately after receiving a character with an error. it will again re-issue the interrupt (if the first one has been cleared by reading the lsr register) when the character with the error is on the top of the fifo, meaning the next one to be read out of the fifo. for example, let?s consider an incoming data stream of 0x55, 0xaa, etc. and t hat the character 0xaa has a parity error associated with it. let?s assume that the character 0x55 has not been read out of the fifo yet. the v252 will issue an inte rrupt as soon as the stop bit of the char acter 0xaa is received. the lsr register will have only the fifo error bit (bit [7]) set and none of the other error bits (bit s [4:1]) will be set, since the byte on the top of the fifo is 0x55 which does not have any erro rs associated with it. when this byte has been read out, the v252 will issue another lsr interrupt and this time the lsr regi ster will show the parity bit (bit [2]) set. ? logic 0 = disable the receiver line status interrupt (default). ? logic 1 = enable the receiver line status interrupt. XR17V252 41 rev. 1.0.1 66 mhz pci bus dual uart with power management support ier[1]: tx ready interrupt enable in non-fifo mode, a tx interrupt is issued whenever the thr is empty. in the fifo mode, an interrupt is issued twice: once when the number of bytes in the tx fifo falls below the programmed trigger level and again when the tx fifo becomes empty. when autors485 mode is enabled (fctr bit [5] = 1), the second interrupt is delayed until the transmitter (both t he tx fifo and the tx shift register) is empty. ? logic 0= disable transmit ready interrupt (default). ? logic 1 = enable transmit ready interrupt. ier[0]: rx interrupt enable the receive data ready in terrupt will be issued when rhr has a data character in the non-fifo mode or when the receive fifo has reached the programmed trigger level in the fifo mode. ? logic 0 = disable the receive data ready interrupt (default). ? logic 1 = enable the receiver data ready interrupt. 5.5 interrupt status register (isr) - read only the uart provides multiple levels of prioritized interrupts to minimize external software interaction. the interrupt status register (isr) provides the user with six interrupt status bits. performing a read cycle on the isr will give the user the current highest pending inte rrupt level to be serviced , others queue up for next service. no other interrupts are acknowledged until t he pending interrupt is serviced. the interrupt source ta b l e , table 15 , shows the data values (bit [5:0 ]) for the six prioritized interrup t levels and the interrupt sources associated with each of these interrupt levels. 5.5.1 interrupt generation: ? lsr is by any of the lsr bits [4:1]. see ier bit [2] description above. ? rxrdy is by rx trigger level. ? rxrdy time-out is by a 4-char plus 12 bits delay timer. ? txrdy is by tx trigger level or tx fifo empty (or transmitter empty in auto rs-485 control). ? msr is by any of the msr bits [3:0]. ? receive xoff/special character is by det ection of a xoff or special character. ? cts#/dsr# is when its transmitter toggles the input pin (from low to high) during auto cts/dsr flow control enabled by efr bit [7] and selection on mcr bit [2]. ? rts#/dtr# is when its receiver toggles the output pin (from low to high) during auto rts/dtr flow control enabled by efr bit [6] and selection on mcr bit [2]. 5.5.2 interrupt clearing: ? lsr interrupt is cleared by a read to the lsr register. ? rxrdy interrupt is cleared by reading data until fifo falls be low the trigger level. ? rxrdy time-out interrupt is cleared by reading rhr. ? txrdy interrupt is cleared by a read to the isr register or writing to thr. ? msr interrupt is cleared by a read to the msr register. ? xoff interrupt is cleared by a read to isr or when xon character(s) is received. ? special character interrupt is cleared by a read to isr or after the next character is received. ? rts#/dtr# and cts#/dsr# status change interrupts are cleared by a read to the msr register. XR17V252 42 66 mhz pci bus dual uart with power management support rev. 1.0.1 ] isr[7:6]: fifo enable status these bits are set to a logic 0 when the fifos are disa bled. they are set to a logic 1 when the fifos are enabled. isr[5:1]: interrupt status these bits indicate the source for a pending interrupt at interrupt priority levels (see table 15 ). see ?section 5.5.1, interrupt generation:? on page 41 and ?section 5.5.2, interrupt clearing:? on page 41 for details. isr[0]: interrupt status ? logic 0 = an interrupt is pending and the isr contents may be used as a pointer to the appropriate interrupt service routine. ? logic 1 = no interrupt pending. (default condition) 5.6 fifo control register (fcr) - write only this register is used to enable the fifos, clear the fi fos, set the transmit/receive fifo trigger levels, and select the dma mode. the dma, and fifo modes are defined as follows: fcr[7:6]: receive fifo trigger select (logic 0 = default, rx trigger level =1) the fctr bits [5:4] are associated with these 2 bits. these 2 bits are used to set the trigger level for the receive fifo. the uart will issue a re ceive interrupt when the number of the charac ters in the fifo crosses the trigger level. table 16 shows the complete selections. note that the receiver and the transmitter cannot use different trigger tables. whichever selection is made last applies to both the rx and tx side. fcr[5:4]: transmit fifo trigger select (requires efr bit [4]=1) (logic 0 = default, tx trigger level = 1) the fctr bits [7:6] are associated with these 2 bits by selecting one of the four tables. the 4 user selectable trigger levels in 4 tables are sup ported for compatibility reas ons. these 2 bits set th e trigger level for the transmit fifo interrup t. the uart will issue a transmit interrupt wh en the number of char acters in the fifo falls below the selected trigger level, or when it gets empty in case that the fifo did not get filled over the trigger level on last re-load. table 16 below shows the selections. t able 15: i nterrupt s ource and p riority l evel p riority isr r egister s tatus b its s ource of the interrupt l evel b it [5] b it [4] b it [3] b it [2] b it [1] b it [0] 1 0 0 0 1 1 0 lsr (receiver line status register) 2 0 0 0 1 0 0 rxrdy (received data ready) 3 0 0 1 1 0 0 rxrdy (receive data time-out) 4 0 0 0 0 1 0 txrdy (transmitter holding register empty) 5 0 0 0 0 0 0 msr (modem status register) 6 0 1 0 0 0 0 rxrdy (received xon/xoff or special character) 7 1 0 0 0 0 0 cts#/dsr#, rts#/dtr# change of state x 0 0 0 0 0 1 none (default) or wake-up indicator XR17V252 43 rev. 1.0.1 66 mhz pci bus dual uart with power management support fcr[3]: dma mode select this bit has no effect since txrdy and rxrdy pins are no t available in this device. it is provided for legacy software compatibility. ? logic 0 = set dma to mode 0 (default). ? logic 1 = set dma to mode 1. fcr[2]: tx fifo reset this bit is only active when fcr bit [0] is active. ? logic 0= no transmit fifo reset (default). ? logic 1 = reset the transmit fifo pointers and fifo level counter logic (the transmit shift register is not cleared or altered). this bit will return to a logic 0 after resetting the fifo. fcr[1]: rx fifo reset this bit is only active when fcr bit [0] is active. ? logic 0 = no receive fifo reset (default). ? logic 1 = reset the receive fifo pointers and fifo level counter logic (the receive shift register is not cleared or altered). this bit will return to a logic 0 after resetting the fifo. fcr[0]: tx and rx fifo enable ? logic 0 = disable the transmit and receive fifo (default). ? logic 1 = enable the transmit and receive fifos. this bit must be set to logic 1 when other fcr bits are written or they will not be programmed. XR17V252 44 66 mhz pci bus dual uart with power management support rev. 1.0.1 5.7 line control register (lcr) - read/write the line control register is used to specify the asynchronous data communication format. the word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. lcr[7]: baud rate divisors enable baud rate generator divisor (dll, dlm, dld) enable. ? logic 0 = data registers are selected (default). ? logic 1 = divisor latch registers (dll, dlm and dld) are selected. lcr[6]: transmit break enable when enabled the break control bit causes a break condition to be transmitted (the tx output is forced to a ?space?, low, state). this condition remains until disabled by setting lcr bit [6] to a logic 0. ? logic 0 = no tx break condition. (default) ? logic 1 = forces the transmitter output (tx) to a ?space ?, logic 0, for alerting the remote receiver of a line break condition. t able 16: t ransmit and r eceive fifo t rigger t able and l evel s election t rigger t able fctr bit [7] fctr bit [6] fcr bit [7] fcr bit [6] fcr bit [5] fcr bit [4] r eceive t rigger l evel t ransmit t rigger l evel c ompatibility ta b l e - a 0 0 0 0 1 1 0 1 0 1 0 0 1 (default) 4 8 14 1 (default) 16c550, 16c2550, 16c2552, 16c554, 16c580, 16l580 ta b l e - b 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 8 16 24 28 16 8 24 30 16c650a, 16l651 table-c 1 0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 8 16 56 60 8 16 32 56 16c654 table-d 1 1 x x x x programmable via rxtrg register programmable via txtrg register 16l2752, 16l2750, 16c2852, 16c850, 16c854, 16c864 XR17V252 45 rev. 1.0.1 66 mhz pci bus dual uart with power management support lcr[5]: tx and rx parity select if the parity bit is enabled, lcr bit [5] selects the forc ed parity format. ? lcr bit [5] = logic 0, parity is not forced (default). ? lcr bit [5] = logic 1 and lcr bit [4] = logic 0, parity bi t is forced to a logical 1f or the transmit and receive data. ? lcr bit [5] = logic 1 and lcr bit [4] = logic 1, parity bit is forced to a logical 0 for the transmit and receive data. lcr[4]: tx and rx parity select if the parity bit is enabled with lcr bi t [3] set to a logic 1, lcr bit [4] se lects the even or odd parity format. ? logic 0 = odd parity is generated by forcing an odd number of logic 1?s in the transmitted character. the receiver must be programmed to check the same format (default). ? logic 1 = even parity is gene rated by forcing an even th e number of logic 1?s in the transmitted character. the receiver must be programmed to check the same format. lcr[3]: tx and rx parity select parity or no parity can be selected via this bit. the pa rity bit is a simple way used in communications for data integrity check. see table 17 above for parity selection summary. ? logic 0 = no parity. ? logic 1 = a parity bit is generated during the transmissi on while the receiver checks for parity error of the data character received. lcr[2]: tx and rx stop-bit length select the length of stop bit is specified by this bit in conjunction with the programmed word length. t able 17: p arity p rogramming lcr bit [5] lcr bit [4] lcr bit [3] p arity selection x x 0 no parity 0 0 1 odd parity 0 1 1 even parity 1 0 1 force parity to mark, ?1? 1 1 1 forced parity to space, ?0? bit [2] w ord length s top bit length (b it time ( s )) 0 5,6,7,8 1 (default) 1 5 1-1/2 1 6,7,8 2 XR17V252 46 66 mhz pci bus dual uart with power management support rev. 1.0.1 lcr[1:0]: tx and rx word length select these two bits specify the word length to be transmitted or received. 5.8 modem control regist er (mcr) - read/write the mcr register is used for controlling the modem interface sign als or general purpo se inputs/outputs. mcr[7]: clock prescaler select (requires efr bit [4]=1) ? logic 0 = divide by one. the input clock from the crysta l or external clock is fed directly to the programmable baud rate generator without further modification, i.e., divide by one (default). ? logic 1 = divide by four. the prescaler divides the input clock from the crystal or external clock by four and feeds it to the programmable baud rate generator, hence, data rates become one forth. mcr[6]: infrared encoder/decoder enable (requires efr bit [4]=1) the state of this bit depends on the sampled logic level of pin enir during power up, following a hardware reset (rising edge of rst# input). afterward user can override this bit for desired operation. ? logic 0 = enable the standard modem receive and transmit character interface. ? logic 1 = enable infrared irda receive and transmit inputs/outputs. while in this mode, the tx/rx output/ input are routed to the infr ared encoder/deco der. the data input and output le vels will confor m to the irda infrared interface requir ement. as such, while in th is mode the infr ared tx output will be a low during idle data conditions. fctr bit [4] may be selected to inve rt the rx input signal level going to the decoder for infrared modules that provide rather an inverted output. mcr[5]: xon-any enable (requires efr bit [4]=1) ? logic 0 = disable xon-any function (default). ? logic 1 = enable xon-any function. in this mode any rx character rece ived will enable xon, resume data transmission. mcr[4]: internal loopback enable ? logic 1 = disable loopback mode (default). ? logic 1 = enable local loopback mode, see loopback section and figure 14 . bit [1] bit [0] w ord length 0 0 5 (default) 0 1 6 1 0 7 1 1 8 XR17V252 47 rev. 1.0.1 66 mhz pci bus dual uart with power management support mcr[3]: send char immediate (op2 in local loopback mode) this bit is used to transmit a character immediately irrespective of the bytes currently in the transmit fifo. the data byte must be loaded into the transmit holding regist er (thr) immediately following the write to this bit (to set it to a ?1?). in other words, no other register must be accessed between setting this bit and writing to the thr. the loaded byte will be transmitted ahead of all t he bytes in the tx fifo, immediately after the character currently being shifted out of the transmit shift register is sent out. the existing lin e parameters (parity, stop bits) will be used when compos ing the character. this bit is self clearing, therefore, must be set before sending a custom character each time. please note that the transm itter must be enabled for th is function (msr[3] = 0). also, if software flow control is enabled, the software fl ow control characters (xon, xoff) have higher priority and will get shifted ou t before the cu stom byte is transmitted. ? logic 0 = send char immediate disabled (default). ? logic 1 = send char immediate enabled. in local loopback mode (mcr[4] = 1), this bit acts as the legacy op2 output and controls the cd bit in the msr register as shown in figure 14 . please make sure that this bit is a ?0? when exiting the local loopback mode. mcr[2]: dtr# or rts# for auto flow control (op1 in local loopback mode) dtr# or rts# auto hardware flow control select. this bi t is in effect only when auto rts/dtr is enabled by efr bit [6]. dtr# selection is associat ed with dsr# and rts# is with cts#. ? logic 0 = uses rts# and cts# pins for auto hardware flow control. ? logic 1 = uses dtr# and dsr# pins for auto hardware flow control. in local loopback mode (mcr[4] = 1), this bit acts as t he legacy op1 output and cont rols the ri bit in the msr register, as shown in figure 14 . mcr[1]: rts# output the rts# pin may be used for automatic hardware flow co ntrol by enabled by efr bit [6] and mcr bit [2]=0. if the modem interface is not used, this output may be used for general purpose. ? logic 0 = force rts# output to a high (default). ? logic 1= force rts# output to low. mcr[0]: dtr# output the dtr# pin may be used for automatic hardware flow control enabled by efr bit [6] and mcr bit [2]=1. if the modem interface is not used, this output may be used for general purpose. ? logic 0 = force dtr# output to a high (default). ? logic 1 = force dtr# output to a low. 5.9 line status register (lsr) - read only this register provides the status of data transfers between the uart and the host. if ier bit [2] is set to a logic 1, an lsr interrupt w ill be generated immediately wh en any character in the rx fifo has an error (parity, framing, overrun, break). lsr[7]: receive fifo data error flag ? logic 0 = no fifo error (default). ? logic 1 = an indicator for the sum of all error bits in the rx fifo. at least one parity error, framing error or break indication is in the fifo data. this bit cl ears when there are no more errors in the fifo. XR17V252 48 66 mhz pci bus dual uart with power management support rev. 1.0.1 lsr[6]: transmitter empty flag this bit is the transmitter empty indica tor. this bit is set to a logic 1 when ever both the transmit fifo (or thr, in non-fifo mode) and the transmit shift register (tsr) ar e both empty. it is set to logic 0 whenever either the tx fifo or tsr contains a data character. lsr[5]: transmit fifo empty flag this bit is the transmit fifo empty indicator. this bit indicates that the transmitter is ready to accept a new character for transmission. this bit is set to a logic high when the last data byte is transferred from the transmit fifo to the transmit shift register. the bit is reset to logic 0 as soon as a data byte is loaded into the transmit fifo. in the non-fifo mode th is bit is set when the transmit hold ing register (thr) is empty; it is cleared when at a byte is written to the thr. lsr[4]: receive break flag ? logic 0 = no break condition (default). ? logic 1 = the receiver received a break signal (rx was low for one character frame time). in the fifo mode, only one break character is loaded into the fifo. the break indication remains until the rx input returns to the idle cond ition, ?mark? or high. lsr[3]: receive data framing error flag ? logic 1 = no framing error (default). ? logic 1 = framing error. the receive character did not hav e a valid stop bit(s). this error is associated with the character available for reading in rhr. lsr[2]: receive data parity error flag ? logic 0 = no parity error (default). ? logic 1 = parity error. the receive character in rhr (top of the fifo) does not have correct parity information and is suspect. this error is associated with the char acter available for reading in rhr. lsr[1]: receiver overrun flag ? logic 0 = no overrun error (default). ? logic 1 = overrun error. a data overrun error condition occurred in the receive shift register. this happens when additional data arrives while the fi fo is full. in this case the previous data in the receive shift register is overwritten. note that under this condition the data byte in the receive shift register is not transferred into the fifo, therefore the data in the fifo is not corrupted by the error. lsr[0]: receive data ready indicator ? logic 0 = no data in receive holding register or fifo (default). ? logic 1 = data has been received and is saved in the receive holding register or fifo. 5.10 modem status register (msr) - read only this register provides the current state of the modem interface signals, or othe r peripheral device that the uart is connected. lower four bits of this register are used to indicate the changed information. these bits are set to a logic 1 whenever a signal from the modem changes state. these bits may be used as general purpose inputs/outputs when they are not used with modem signals. msr[7]: cd input status normally this bit is the complement of the cd# input. in the loopback mode this bit is equivalent to bit [3] in the mcr register. the cd# input may be used as a general purpose input when the modem interface is not used. XR17V252 49 rev. 1.0.1 66 mhz pci bus dual uart with power management support msr[6]: ri input status normally this bit is the complement of the ri# input. in the loopback mode this bit is equivalent to bit [2] in the mcr register. the ri# input may be used as a general purpose input when the modem interface is not used. msr[5]: dsr input status dsr# pin may function as automatic hardware flow contro l signal input if it is enabled and selected by auto cts/dsr bit (efr bit [6]=1) and rts/dtr flow control select bit (mcr bit [2]=1). auto cts/dsr flow control allows starting and stopping of local data transmissi ons based on the modem dsr# signal. a high on the dsr# pin will stop uart transmitter as soon as the curren t character has finished transmission, and a low will resume data transmissi on. normally msr bit [5] is the complement of the dsr# input. however in the loopback mode, this bit is equivalent to the dtr# bit in the mcr register. the dsr# input may be used as a general purpose input when the modem interface is not used. msr[4]: cts input status cts# pin may function as automatic hardware flow control signal input if it is enabled and selected by auto cts/dsr bit (efr bit [6]=1) and rts/dtr flow control select bit (mcr bit [2]=0). auto cts/dsr flow control allows starting and stopping of local data transmissions based on the modem cts# signal. a high on the cts# pin will stop uart transmitter as soon as the current character has finished transmission, and a low will resume data transmission. norma lly msr bit [4] is the complement of the cts# input. however in the loopback mode, this bit is equivalent to the rts# bit in the mcr register. the cts# input may be used as a general purpose input when the modem interface is not used. msr[3]: delta cd# input flag ? logic 0 = no change on cd# input (default). ? logic 1 = indicates that the cd# input has changed st ate since the last time it was monitored. a modem status interrupt will be generated if msr interrupt is enabled (ier bit [3]). msr[2]: delta ri# input flag ? logic 0 = no change on ri# input (default). ? logic 1 = the ri# input has changed from a low to a high, ending of the ringing signal. a modem status interrupt will be ge nerated if msr in terrupt is enabled (ier bit [3]). msr[1]: delta dsr# input flag ? logic 0 = no change on dsr# input (default). ? logic 1 = the dsr# input has changed state since the last time it was monitored. a modem status interrupt will be generated if msr interrup t is enabled (ier bit [3]). msr[0]: delta cts# input flag ? logic 0 = no change on cts# input (default). ? logic 1 = the cts# input has changed state since the la st time it was monitored. a modem status interrupt will be generated if msr interrup t is enabled (ier bit [3]). 5.11 modem status register (msr) - write only the upper four bits [7:4] of this register set the delay in number of bits time for the auto rs-485 turn around from transmit to receive. msr [7:4]: auto rs485 turn-around delay (requires efr bit [4]=1) when auto rs485 feature is enabled (fctr bit [5]=1) an d rts# output is connected to the enable input of a rs-485 transceiver. these 4 bits select from 0 to 15 bit-time delay after the end of the last stop-bit of the last transmitted character. this delay controls when to change th e state of rts# output. this delay is very useful in long-cable networks. table 18 shows the selection. the bits are enabled by efr bit [4]. XR17V252 50 66 mhz pci bus dual uart with power management support rev. 1.0.1 msr [3]: transmitter disable this bit can be used to disable the transmitter by halting the transmit shift register (t sr). when this bit is set to a ?1?, the bytes already in the fifo will not be sent out. also, any more data loaded into the fifo will stay in the fifo and will not be sent out. when this bit is set to a ?0?, the bytes currently in the tx fifo will be sent out. please note that setting this bit to a ?1? stops any character from going out. also , this bit must be a ?0? for send char immediate function (see mcr[3]). ? logic 0 = enable transmitter (default). ? logic 1 = disable transmitter. t able 18: a uto rs485 h alf - duplex d irection c ontrol d elay from t ransmit - to -r eceive msr[7] msr[6] msr[5] msr[4] d elay in d ata b it ( s ) t ime 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 9 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 1 0 0 1 9 1 0 1 0 10 1 0 1 1 11 1 1 0 0 12 1 1 0 1 13 1 1 1 0 14 1 1 1 1 15 XR17V252 51 rev. 1.0.1 66 mhz pci bus dual uart with power management support msr [2]: receiver disable this bit can be used to disable the receiver by halting th e receive shift register (rsr). when this bit is set to a logic 1, the receiver will operat e in one of the following ways: if a character is be ing received at the time of se tting this bit, that character will be co rrectly received. no more characters will be received. if the receiver is idle at the time of setting this bi t, no characters will be received. the receiver can be enabled an d will start receiving characte rs by resetting this bit to a logic 0. the receiver will operate in one of the following ways: if the receiver is idle (rx pin is hi gh) at the time of setti ng this bit, the next ch aracter will be received normally. it is recommended that the receiver be idle when resetting this bit to a logic 0. if the receiver is not idle (rx pin is toggling) at the time of setting this bit, the rx fifo will be filled with unknown data. any data that is in the rx fifo can be read out at any time whether the re ceiver is disabled or not. ? logic 0 = enable receiver (default). ? logic 1 = disable receiver. msr [1:0]: reserved 5.12 scratch pad register (spr) - read/write this is a 8-bit general purpose register for the user to store temporary data. the content of this register is preserved during sleep mode but becomes 0xff (default) after a reset or a power off-on cycle. 5.13 feature control register (fctr) - read/write fctr[7:6]: tx and rx fifo trigger table select these 2 bits select the transmit and receive fifo trigger level table a, b, c or d. when table a, b, or c is selected the auto rts flow c ontrol trigger level is set to "next fifo trigger level" for compatibility to st16c550 and st16c650 series. rts/dtr# triggers on the next level of the rx fifo trigger level, in another word, one fifo level above and one fifo level below. see table 16 for complete selection with fcr bit [5:4] and fctr bits [7:6], i.e. if table c is used on the receiver with rx fifo trigger level set to 56 bytes, rts/dtr# output will de-assert at 60 and re-assert at 16. fctr[5]: auto rs485 enable auto rs485 half duplex control enable/disable. ? logic 0 = standard st16c550 mode. transmitter generates an interrupt when transmit holding register (thr) becomes empty. transmit shift regist er (tsr) may still be shifting data bit out. ? logic 1 = enable auto rs485 half duplex direction co ntrol. rts# output changes from high to low when finished sending the last stop bit of the last character out of the tsr register. it changes from low to high when a data byte is loaded into the thr or transmit fifo. the change to high occurs prior sending the start-bit. it also changes the transmitter interrupt from transmit holding to transmit shift register (tsr) empty. fctr[4]: infrared rx input logic select ? logic 0 = select rx input as active high encoded irda data, normal (default). ? logic 1 = select rx input as active low encoded irda data, inverted. XR17V252 52 66 mhz pci bus dual uart with power management support rev. 1.0.1 fctr [3:0] - auto rts/dtr fl ow control hysteresis select these bits select the auto rts/dtr flow control hyster esis and only valid when tx and rx trigger table-d is selected (fctr bit [7:6] are set to logic 1). the rts/dtr hysteresis is referenced to the rx fifo trigger level. after reset, these bits are set to logic 0 selecting the next fifo trigger level for hardware flow control. table 19 below shows the 16 selectab le hysteresis levels. 5.14 enhanced feature register (efr) - read/write enhanced features are enabled or disabled using this register. bits [3:0] provide single or dual consecutive character software flow control selection (see table 20 ). when the xon1 and xon2 and xoff1 and xoff2 modes are selected, the double 8-bit words are concatenated in to two sequential characters. caution: note that whenever changing the tx or rx flow control bits, always reset all bits back to logic 0 (disable) before programming a new setting. efr[7]: auto cts flow control enable automatic cts or dsr flow control. ? logic 0 = automatic cts/dsr flow control is disabled (default). ? logic 1 = enable automatic cts/dsr flow control. transmission stops when cts/dsr# pin de-asserts (high). transmission resumes when cts/dsr# pin is as serted (low). the selection for cts# or dsr# is through mcr bit [2]. t able 19: 16 s electable h ysteresis l evels w hen t rigger t able -d is s elected fctr b it [3] fctr b it [2] fctr b it [1] fctr b it [0] rts/dtr h ysteresis ( characters ) 0 0 0 0 0 0 0 0 1 +/- 4 0 0 1 0 +/- 6 0 0 1 1 +/- 8 0 1 0 0 +/- 8 0 1 0 1 +/- 16 0 1 1 0 +/- 24 0 1 1 1 +/- 32 1 1 0 0 +/- 12 1 1 0 1 +/- 20 1 1 1 0 +/- 28 1 1 1 1 +/- 36 1 0 0 0 +/- 40 1 0 0 1 +/- 44 1 0 1 0 +/- 48 1 0 1 1 +/- 52 XR17V252 53 rev. 1.0.1 66 mhz pci bus dual uart with power management support efr[6]: auto rts or dtr flow control enable rts#/dtr# output may be used for hardware flow control by setting efr bit [6] to logic 1. when auto rts/ dtr is selected, an in terrupt will be gener ated when the receive fifo is f illed to the progra mmed trigger level and rts/dtr# will de-assert (high) at the next upper trigger or selected hysteresis le vel. rts/dtr# will re- assert (low) when fifo data falls below the next lower trigger or selected hysteres is level (see fctr bits 4- 7). the rts# or dtr# output must be asserted (low) before the auto rts/dtr can take effect. the selection for rts# or dtr# is through mcr bi t [2]. rts/dtr# pin will function as a general purpo se output when hardware flow control is disabled. ? logic 0 = automatic rts/dtr flow control is disabled (default). ? logic 1 = enable automatic rts/dtr flow control. efr[5]: special character detect enable ? logic 0 = special character detect disabled (default). ? logic 1 = special character detect enabled. the uart compares each incoming receive character with data in xoff-2 register. if a match ex ists, the received data will be transfer red to fifo and isr bit [4] will be set to indicate detection of the special character. bit [0] corresponds with the lsb bit for the receive character. if flow control is set for comparing xon1, xoff1 (efr [1:0]=10) then flow control and special character work normally. however, if flow control is set for comparing xon2, xoff2 (efr[1:0]=01) then flow control works norma lly, but xoff2 will not go to the fifo, and will generate an xoff interrupt and a special character interrupt. efr[4]: enhanced function bits enable enhanced function control bit. this bit enables the enhance d functions in ier bits [7:5], isr bits [5:4], fcr bits [5:4], mcr bits [7:5,3:2] and msr [7:2] bits to be modified. after modifying any enhanced bits, efr bit [4] can be set to a logic 0 to latch the new values. this feature prevents legacy software from altering or overwriting the enhanced functions once set. norma lly, it is recommended to leave it enabled, high. ? logic 0 = modification disable/latch e nhanced features. ier bits [7:5], isr bits [5:4], fcr bits [5:4], mcr bits [7:5, 3:2] and msr [7:2] bits are saved to retain the user settings. afte r a reset, all these bits are set to a logic 0 to be compatible with st16c550 mode (default). ? logic 1 = enables the enhanced functions. when this bit is set to a logic 1 all enhanced features are enabled. XR17V252 54 66 mhz pci bus dual uart with power management support rev. 1.0.1 efr[3:0]: software flow control select combinations of software flow control can be selected by programming these bits, as shown in table 20 below. 5.15 txcnt[7:0]: transmit fifo level counter - read only transmit fifo level byte count from 0x00 (low) to 0x40 (64). this 8-bit register gives an indication of the number of characters in the transmit fifo. the fifo le vel byte count register is read only. the user can take advantage of the fifo level byte counter for faster data loading to the transmit fifo, which reduces cpu bandwidth requirements. 5.16 txtrg [7:0]: transmit fi fo trigger level - write only an 8-bit value written to this register sets the tx fifo trigger level from 0x00 (zero) to 0x40 (64). the tx fifo trigger level generates an interrupt whenever the data leve l in the transmit fifo falls below this preset trigger level. 5.17 rxcnt[7:0]: receive fifo level counter - read only receive fifo level byte count from 0x00 (zero) to 0x40 (64). it gives an indication of the number of characters in the receive fifo. the fifo level byte count register is read only. the user can take advantage of the fifo level byte counter for faster data unloading from the receiver fifo, which reduces cpu bandwidth requirements. 5.18 rxtrg[7:0]: receive fifo trigger level - write only an 8-bit value written to this register, sets the rx fifo trigger level from 0x00 (zero) to 0x40 (64). the rx fifo trigger level generates an interrupt whenever the receive fifo level rises to this preset trigger level. 5.19 xoff1, xoff2, xon1 and xon2 registers, write only these registers are used to program the xoff1, xoff 2, xon1 and xon2 control characters respectively. t able 20: s oftware f low c ontrol f unctions efr bit [3] efr bit [2] efr bit [1] efr bit [0] t ransmit and r eceive s oftware f low c ontrol 0 0 0 0 no tx and rx flow control (default and reset) 0 0 x x no transmit flow control 1 0 x x transmit xon1, xoff1 0 1 x x transmit xon2, xoff2 1 1 x x transmit xon1 and xon2, xoff1 and xoff2 x x 0 0 no receive flow control x x 1 0 receiver compares xon1, xoff1 x x 0 1 receiver compares xon2, xoff2 1 0 1 1 transmit xon1, xoff1 receiver compares xon1 or xon2, xoff1 or xoff2 0 1 1 1 transmit xon2, xoff2 receiver compares xon1 or xon2, xoff1 or xoff2 1 1 1 1 transmit xon1 and xon2, xoff1 and xoff2 receiver compares xon1 and xon2, xoff1 and xoff2 0 0 1 1 no transmit flow control receiver compares xon1 and xon2, xoff1 and xoff2 XR17V252 55 rev. 1.0.1 66 mhz pci bus dual uart with power management support 5.20 xchar register, read only this register gives the status of the last sent contro l character (xon or xoff) and the last received control character (xon or xoff). this register will be reset to 0x 00 if, at anytime, the softwa re flow control is disabled. xchar [7:4]: reserved xchar [3]: transmit xon indicator if the last transmitted control character was a xon char acter or characters (xon1, xo n2), this bit will be set to a logic 1. this bit will clear after the read. xchar [2]: transmit xoff indicator if the last transmitted control character wa s a xoff character or characters (xof f1, xoff2), this bit will be set to a logic 1. this bit will clear after the read. xchar [1]: xon detect indicator if the last received control character was a xon character or characters (xon1 , xon2), this bit will be set to a logic 1. this bit will clear after the read. xchar [0]: xoff detect indicator if the last received cont rol character was a xoff charac ter or characters (xoff1, xoff 2), this bit will be set to a logic 1. this bit will clear after the read. XR17V252 56 66 mhz pci bus dual uart with power management support rev. 1.0.1 t able 21: uart reset conditions registers reset state i/o signals reset state dll bits [7:0] = 0x01 tx[ch-1:0] high dlm bits [7:0] = 0x00 irtx[ch-1:0] low dld bits [7:0] = 0x00 rts#[ch-1:0] high rhr bits [7:0] = 0xxx dtr#[ch-1:0] high thr bits [7:0] = 0xxx eeck low ier bits [7:0] = 0x00 eecs low fcr bits [7:0] = 0x00 eedi low isr bits [7:0] = 0x01 lcr bits [7:0] = 0x00 mcr bits [7:0] = 0x00 lsr bits [7:0] = 0x60 msr bits [3:0] = logic 0 bits [7:4] = logic levels of the inputs spr bits [7:0] = 0xff fctr bits [7:0] = 0x00 efr bits [7:0] = 0x00 tfcnt bits [7:0] = 0x00 tftrg bits [7:0] = 0x00 rfcnt bits [7:0] = 0x00 rftrg bits [7:0] = 0x00 xchar bits [7:0] = 0x00 xon1 bits [7:0] = 0x00 xon2 bits [7:0] = 0x00 xoff1 bits [7:0] = 0x00 xoff2 bits [7:0] = 0x00 XR17V252 57 rev. 1.0.1 66 mhz pci bus dual uart with power management support absolute maximum ratings power supply range 4 volts voltage at any pin -0.5 to 4v operating temperature -40 o to +85 o c storage temperature -65 o to +150 o c package dissipation 500 mw thermal resistance (14x14x1.0mm 100-tqfp) theta-ja = 42, theta-jc = 8 electrical characteristics dc electrical characteristics ta=-40 o to +85 o c ( industrial grade ) s upply v oltage , vcc = 3.0 - 3.6v s ymbol p arameter m in m ax u nit s c ondition n otes v il input low voltage -0.5 0.3vcc v for pci bus inputs -0.5 0.8 v for non-pci bus inputs v ih input high voltage 0.5vcc vcc + 0.5 v for pci bus inputs 2.0 6.0 v for non-pci bus inputs 5v tolerant inputs 2.0 vcc + 0.5 for external clock (xtal1) input only not 5v tolerant v ol output low voltage 0.1vcc v i ol = 1.5ma pci bus outputs 0.4 v i ol = 6ma non-pci bus outputs v oh output high voltage 0.9vcc v i oh = -0.5ma pci bus outputs 2.4 v i oh = -2ma non-pci bus outputs i il input leakage current 10 a 0 < v in < vcc i cl input clock leakage 10 a c in input pin capacitance 10 pf c clk clk pin capacitance 5 12 pf c idsel idsel pin capacitance 8 pf i off pme# input leakage - 1 a v o 3.6v, vcc off or floating i cc power supply current 4 ma pci bus clk and ext. clock = 2mhz, all inputs at vcc or gnd and all outputs are unloaded. i sleep sleep current 1 ma both uarts asleep. ad[31:0] at gnd, all inputs at vcc or gnd. XR17V252 58 66 mhz pci bus dual uart with power management support rev. 1.0.1 ac electrical characteristics ta=-40 o to +85 o c ( industrial grade ) vcc = 3.0 - 3.6v s ymbol p arameter m in m ax u nits n otes xtal1 uart crystal oscillator 24 mhz on-chip osc. eclk external clock 64 mhz i oh(ac, min) switching current high, min -12vcc ma v out = 0.3vcc i oh(ac, max) switching current high, max -32vcc ma v out = 0.7vcc i ol(ac, min) switching current low, min 16vcc ma v out = 0.6vcc i ol(ac, max) switching current low, max 38vcc ma v out = 0.18vcc i ch high clamp current 25+(vin-vcc-1)/0.015 ma vcc+4 > vin vcc+1 i cl low clamp current -25+(vin+1)/0.015 ma -3 < vin -1 slew r output rise slew rate 1 4 v/ns 0.3vcc to 0.6vcc slew f output fall slew rate 1 4 v/ns 0.6vcc to 0.3vcc t cyc clk cycle time 15 ns pci bus clock, clk up to 66.67mhz t high clk high time 6 ns t low clk low time 6 ns clk slew rate 1.5 4 v/ns t val clk to signal valid delay 2 6 ns bused and point to point signals t on float to active delay 2 ns t off active to float delay 14 ns t su input setup time to clk - bused signals 3 ns t su (ptp) input setup time to clk - point to point signals 5 ns t h input hold time from clk 0 ns t rst rst# active time after power stable 1 ms t rst-clk# rst# active time after clk stable 100 us t rst-off reset active to output float delay 40 ns t rhfa rst# high to first configu - ration access 2 25 clocks t rhff rst# high to first frame# assertion 5 clocks rst# slew rate 50 mv/ns XR17V252 59 rev. 1.0.1 66 mhz pci bus dual uart with power management support f igure 19. pci b us c onfiguration s pace r egisters r ead and w rite operation clk frame# ad[31:0] c/be[3:0]# trdy# irdy# devsel# 123 4 cfg-rd byte enable# pcicfg_rd host host host host host target target target data transfer address data clk frame# ad[31:0] c/be[3:0]# trdy# irdy# devsel# 123 4 cfg-wr byte enable# pcicfg_wr host host host host host target target target data transfer address write data XR17V252 60 66 mhz pci bus dual uart with power management support rev. 1.0.1 f igure 20. d evice c onfiguration and uart r egisters r ead o peration for a b yte or dword clk frame# ad[31:0] c/be[3:0]# trdy# irdy# devsel# 1 23 4 address bus cmd byte enable# = byte byte transfer pci_rd1 5 6 7 par perr# 8 note: perr# and serr are optional in a bus target application. even parity is on ad[31:0], c/be[3:0]#, and par data parity active host host host host host target host target target target data byte wait wait wait address parity serr# target targe t active data word byte enable# = dword dword transfer wait wait data parity active 91011 XR17V252 61 rev. 1.0.1 66 mhz pci bus dual uart with power management support f igure 21. d evice c onfiguration registers , uart r egisters and t ransmit d ata b urst w rite o pera - tion clk frame# ad[31:0] c/be[3:0]# trdy# irdy# devsel# 1 23 4 address bus cmd byte enable# = dword pci bwr 5 6 7 par perr# 8 note: perr# and serr are optional in a bus target application. even parity is on ad[31:0], c/be[3:0]#, and par host host host host host target host target target target address parity serr# target target active data parity active 910 data dword data dword dword transfer dword transfer dword transfer dword transfer dword transfer data parity data parity data parity data parity active active active active 11 data dword data dword data dword XR17V252 62 66 mhz pci bus dual uart with power management support rev. 1.0.1 f igure 22. d evice c onfiguration r egisters , uart r egisters and r eceive d ata b urst r ead o peration data clk frame# ad[31:0] c/be[3:0]# trdy# irdy# devsel# 1 13 ad bus cmd byte enable# = dword pci_brd par perr# 18 note: perr# and serr are optional in a bus target application. even parity is on ad[31:0], c/be[3:0]#, and par host host host host host target host target target target serr# target target dword transfer dword transfer dword transfer dword transfer 23 8 ad data data data data active active active active active data data data XR17V252 63 rev. 1.0.1 66 mhz pci bus dual uart with power management support f igure 23. 3.3v pci b us c lock (dc to 66mh z ) 0.4 vcc, p-to-p (minimum) 0.6vcc 0.2vcc clk output delay tri-state output t_val t_on t_off t_su t_h pci_clk inputs valid t_cyc t_high t_low 0.5vcc 0.4vcc 0.3vcc v_trise v_tfall input v_th v_tl v_test v_max measurement condition parameters vth = 0.6vcc vtl = 0.2vcc vtest = 0.4vcc vtrise = 0.285vcc vtfall = 0.615vcc vmax = 0.4vcc input signal slew rate = 1.5 v/ns XR17V252 64 66 mhz pci bus dual uart with power management support rev. 1.0.1 f igure 24. t ransmit d ata i nterrupt at t rigger l evel f igure 25. r eceive d ata r eady i nterrupt at t rigger l evel stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 5 data bits 6 data bits 7 data bits start bit tx data next data start bit tx interrupt at transmit trigger level baud rate clock of 16x or 8x txnofifo- 1 set at below trigger level clear at above trigger level stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 start bit rx data input first byte that reaches the trigger level rx data ready interrupt at receive trigger level rxfifo1 de-asserted at below trigger level asserted at above trigger level XR17V252 65 rev. 1.0.1 66 mhz pci bus dual uart with power management support package dimensions 26 50 51 75 100 76 100 lead thin quad flat pack (14 x 14 x 1.0 mm, tqfp) d d 1 d d 1 e 1 25 seating plane a 2 a 1 c l a min max min max a 0.039 0. 047 1.00 1.20 a 1 0.002 0.006 0.05 0.15 a 2 0.037 0.041 0.95 1.05 b 0.007 0. 011 0.17 0.27 c 0.004 0. 008 0.09 0.20 d 0.622 0. 638 15. 80 16. 20 d 1 0.547 0.555 13.90 14.10 e 0.020 bsc 0.50 bsc l 0.018 0. 030 0.45 0.75 0 o 7 o 0 o 7 o note: the control dimension is in millimeter. symbol inches millimeters rev. 1.00 b 66 notice exar corporation reserves the right to make changes to the products contained in this publicat ion in order to improve design, performanc e or reliability. exar corp oration assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infr ingement. charts and sche dules contained her e in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully ch ecked; no responsibility, however , is assumed for inaccuracies. exar corporation does not re commend the use of any of its products in life suppo rt applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products ar e not authorized for use in such applications unless exar corporation receives , in writing, assuranc es to its satisfaction that: (a) th e risk of injury or damage has been minimized; (b) th e user assumes all such ris ks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2006 exar corporation datasheet march 2006. send your uart technical inquiry with technical details to hotline: uarttechsupport@exar.com . reproduction, in part or whole, without the prior written consent of exar co rporation is prohibited. XR17V252 66 mhz pci bus dual uart with power management support rev. 1.0.1 revision history d ate r evision d escription february 2006 1.0.0 initial datasheet release. march 2006 1.0.1 corrected maximum external clock frequen cy in ac electrical characteristics. XR17V252 i rev. 1.0.1 66 mhz pci bus dual uart with power management support table of contents general description........... ................ ....................... ................. ................ ............. 1 a pplications ............................................................................................................................... ............... 1 f eatures ............................................................................................................................... ..................... 1 f igure 1. b lock d iagram of the XR17V252 ...................................................................................................................... ......... 1 f igure 2. p in o ut of the XR17V252 ...................................................................................................................... ..................... 2 ordering information ............................................................................................................................... 2 p in d escriptions ............................................................................................................................... ........ 3 pci local bus interface ........................................................................................................ ........... 3 modem or serial i/o interface.................................................................................................. ..... 3 ancillary signals .............................................................................................................. ................. 4 functional description ..... ................ ....................... ................. ................ ............. 6 pci local bus interface........................................................................................................ ...................................... 6 pci local bus configuration space registers ........................................................................................................... 6 power management registers .................................. ................................................................... .............................. 6 eeprom interface .......... .............. .............. .............. .............. ........... ........... ............ ........... ...................................... 6 1.0 XR17V252 internal registers ................................................................................................ ....... 7 f igure 3. t he XR17V252 r egister s ets ............................................................................................................................... ...... 7 1.1 pci local bus configuratio n space registers .......... .............. .............. ........... ............ ........... ....... 7 t able 1: pci l ocal b us c onfiguration s pace r egisters ......................................................................................................... 8 1.2 power management registers ...... .............. .............. .............. .............. .............. ........... .......... .............. 9 t able 2: p ower m anagement r egisters .............................................................................................................................. ...... 9 1.2.1 power states and power state transitions of the v252 ..................................................................... 10 d0 state ....................................................................................................................... ............................................ 10 d3hot state .................................................................................................................... .......................................... 10 d3cold state ................................................................................................................... .......................................... 11 f igure 4. p ower s tate t ransitions of the XR17V252 ........................................................................................................... 11 1.3 special read/write register to store user information ........................................................ 11 t able 3: s pecial r ead /w rite r egister .............................................................................................................................. ....... 11 1.4 eeprom interface ........................................................................................................... ........................... 12 t able 4: eeprom a ddress d efinitions .............................................................................................................................. ..... 12 1.5 device internal register sets .............................................................................................. ............... 12 t able 5: XR17V252 uart and d evice c onfiguration r egisters ........................................................................................... 13 1.6 device configuration re gisters .......... .............. .............. .............. .............. .............. ............. ............ 14 t able 6: d evice c onfiguration r egisters shown in byte alignment ................................................................................... 14 t able 7: d evice c onfiguration r egisters shown in dword alignment .............................................................................. 15 1.6.1 the global interrupt register............................................................................................ ........................... 15 f igure 5. t he g lobal i nterrupt r egister , int0, int1, int2 and int3 .................................................................................. 16 t able 8: uart c hannel [1:0] i nterrupt s ource e ncoding ..................................................................................................... 16 t able 9: uart c hannel [1:0] i nterrupt c learing ................................................................................................................... 16 1.6.2 general purpose 16-bit time r/counter [timermsb, timelsb, ti mer, timecntl] (default 0xxx-xx-00- 00)............................................................................................................................ ....................................................... 17 f igure 6. t imer /c ounter circuit ............................................................................................................................... ................ 17 t able 10: timer control r egisters .............................................................................................................................. ...... 18 timer operation ................................................................................................................ ................................ 18 f igure 7. t imer o utput in o ne -s hot and r e - triggerable m odes .......................................................................................... 19 f igure 8. i nterrupt o utput ( active low) in o ne -s hot and r e - triggerable m odes ............................................................ 20 1.6.3 8xmode [7:0] (default 0x00).............................................................................................. .................................... 20 1.6.4 rega [15:8] reserved ..................................................................................................... ........................................ 20 1.6.5 reset [23:16] - (default 0x00)........................................................................................... .................................... 20 1.6.6 sleep [31:24] (default 0x00) ............................................................................................. .................................... 20 1.6.7 device identification and revision....................................................................................... .......................... 21 1.6.8 regb register ............................................................................................................ ............................................. 21 1.6.9 multi-purpose inputs and outputs ......................................................................................... ....................... 22 1.6.10 mpio register ........................................................................................................... ............................................. 22 f igure 9. m ultipurpose input / output internal circuit ........................................................................................................... 22 2.0 crystal oscillator / buffer................................................................................................ ..... 24 f igure 10. t ypical c rystal connections ............................................................................................................................... .. 24 3.0 transmit and receive data .................................................................................................. ...... 25 3.1 fifo data loading and unloading in 32-bi t format ........... .............. .............. ............... ........... ..... 25 XR17V252 ii 66 mhz pci bus dual uart with power management support rev. 1.0.1 3.1.1 normal rx fifo data unloading at locations 0x100 (channel 0) and 0x300 (channel 1).......... 26 3.1.2 special rx fifo data unloading at locations 0x180 (channel 0) and 0x380 (channel 1) .......... 26 3.1.3 tx fifo data loading at locations 0x100 (channel 0) and 0x300 (channel 1) ................................ 27 3.2 fifo data loading and unloading through the uart channel registers, thr and rhr in 8- bit format..................................................................................................................... .............................. 27 t able 11: t ransmit and r eceive d ata r egister in b yte format , 16c550 compatible .......................................................... 27 4.0 uart ....................................................................................................................... ............................... 28 4.1 programmable baud rate generator with fractional divisor............................................ 28 f igure 11. b aud r ate g enerator ............................................................................................................................... .............. 29 t able 12: t ypical data rates with a 24 mh z crystal or external clock at 16x s ampling ................................................. 29 4.2 automatic hardware (rts/cts or dtr/dsr) fl ow control operation.... ........... ........... ....... 30 f igure 12. a uto rts/dtr and cts/dsr f low c ontrol o peration ...................................................................................... 31 4.3 infrared mode ........... .............. .............. .............. .............. ........... ........... ............ ......... ............................... 32 f igure 13. i nfrared t ransmit d ata e ncoding and r eceive d ata d ecoding .......................................................................... 32 4.4 internal loopback ................ .............. .............. .............. .............. ........... ........... ............ .......................... 33 f igure 14. i nternal l oop b ack ............................................................................................................................... .................. 33 4.5 uart channel conf iguration registers and addr ess decoding .... .............. ............... ......... 33 t able 13: uart channel configuration registers. .................................................................................... .............. 34 t able 14: uart channel configuration registers description. s haded bits are enabled by efr b it -4. ....... 35 4.6 transmitter ................................................................................................................ .................................. 36 4.6.1 transmit holding register (thr).......................................................................................... ........................... 36 4.6.2 transmitter operation in non-fifo mode ................................................................................... ................. 36 f igure 15. t ransmitter o peration in non -fifo m ode ............................................................................................................ 37 4.6.3 transmitter operation in fifo mode ....................................................................................... ...................... 37 4.6.4 auto rs485 operation ..................................................................................................... ..................................... 37 f igure 16. t ransmitter o peration in fifo and f low c ontrol m ode ................................................................................... 38 4.7 receiver ................................................................................................................... ...................................... 38 4.7.1 receiver operation in non-fifo mode ..................................................................................... ..................... 38 f igure 17. r eceiver o peration in non -fifo m ode .................................................................................................................. 38 4.7.2 receiver operation with fifo ............................................................................................. .............................. 39 f igure 18. r eceiver o peration in fifo and f low c ontrol m ode ......................................................................................... 39 5.0 uart configuration registers ............................................................................................... .. 39 5.1 receive holding register (rhr) - read only ......... .............. .............. ........... ........... ............ .......... .. 39 5.2 transmit holding register (thr) - write only............................................................................... . 39 5.3 baud rate generator diviso rs (dlm, dll and dld) ........ .............. .............. .............. .............. ....... 39 5.4 interrupt enable register (ier) - read/write.......... .............. .............. .............. .............. ............. .. 39 5.4.1 ier versus receive fifo interrupt mode operation ......................................................................... ...... 39 5.4.2 ier versus receive/transmit fifo polled mode operation .................................................................. 40 5.5 interrupt status register (isr) - read only......... .............. .............. ........... ........... ............ ......... ... 41 5.5.1 interrupt generation: .................................................................................................... .................................... 41 5.5.2 interrupt clearing: ...................................................................................................... ....................................... 41 t able 15: i nterrupt s ource and p riority l evel ..................................................................................................................... 42 5.6 fifo control register (fcr) - write only................................................................................... ...... 42 t able 16: t ransmit and r eceive fifo t rigger t able and l evel s election .......................................................................... 44 5.7 line control register (lcr) - read/write................................................................................... ...... 44 t able 17: p arity p rogramming .............................................................................................................................. .................... 45 5.8 modem control register (mcr) - read/write .................................................................................. 46 5.9 line status register (lsr) - read only..................................................................................... ......... 47 5.10 modem status register (msr) - read only ................................................................................... .. 48 5.11 modem status register (msr) - write only .................................................................................. .. 49 t able 18: a uto rs485 h alf - duplex d irection c ontrol d elay from t ransmit - to -r eceive ................................................. 50 5.12 scratch pad register (spr) - re ad/write ............. .............. .............. .............. .............. .............. .... 51 5.13 feature control register (fctr) - read/write............................................................................ 5 1 t able 19: 16 s electable h ysteresis l evels w hen t rigger t able -d is s elected ................................................................ 52 5.14 enhanced feature register (efr) - read/write ......... .............. .............. .............. ............... ......... 52 t able 20: s oftware f low c ontrol f unctions ........................................................................................................................ 54 5.15 txcnt[7:0]: transmit fifo level counter - read only ....... .............. .............. ........... ........... ....... 54 5.16 txtrg [7:0]: transmit fifo trig ger level - write only ... .............. .............. .............. ........... ....... 54 5.17 rxcnt[7:0]: receive fifo level co unter - read only.......... .............. .............. ........... ........... ....... 54 5.18 rxtrg[7:0]: receive fifo trigger level - write on ly................................................................... 54 5.19 xoff1, xoff2, xon1 and xon2 regis ters, write only.......... .............. .............. ........... ........... ....... 54 5.20 xchar register, read only ...... .............. .............. .............. .............. .............. ............ ......... ................. 55 t able 21: uart reset conditions .................................................................................................... .................................. 56 XR17V252 iii rev. 1.0.1 66 mhz pci bus dual uart with power management support absolute maximum ratings ............ ................ ............................ .............. ........... 57 electrical characteristics........ ........................ .................. ................ ............. 57 dc electrical characteristics .................................................................................................. 57 ta=-40o to +85oc (industrial grade) supply voltage, vcc = 3.0 - 3.6v ......... .............. .............. ............ .......... ...... 57 ac electrical characteristics.................................................................................................. . 58 ta=-40o to+85oc (industrial grade) vcc = 3.0 - 3.6v.... .............. .............. ........... ........... ........... ........... ................. 58 f igure 19. pci b us c onfiguration s pace r egisters r ead and w rite operation ................................................................. 59 f igure 20. d evice c onfiguration and uart r egisters r ead o peration for a b yte or dword ...................................... 60 f igure 21. d evice c onfiguration registers , uart r egisters and t ransmit d ata b urst w rite o peration ..................... 61 f igure 22. d evice c onfiguration r egisters , uart r egisters and r eceive d ata b urst r ead o peration ........................ 62 f igure 23. 3.3v pci b us c lock (dc to 66mh z ) ....................................................................................................................... 63 f igure 24. t ransmit d ata i nterrupt at t rigger l evel ........................................................................................................... 64 f igure 25. r eceive d ata r eady i nterrupt at t rigger l evel ................................................................................................. 64 package dimensions ......... ................. ................ ................... .............. ............ ........ 65 r evision h istory ............................................................................................................................... ...... 66 table of contents .......... ................ ................. ................ .............. .............. .............. i |
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